Intel PXA255 - Manual (Page 387)

Intel® PXA255 Processor Developer’s Manual 11-3
Fast Infrared Communication Port
11.2.2 Frame Format
The frame format used with 4-Mbps transmission is shown in Figure 11-3 .
The preamble, start, and stop flags are a mixture of chips that contain 0, 1, or 2 pulses in their
timeslots. Chips with 0 and 2 pulses are used to construct flags because the chips represent invalid
data bit pairings. The preamble contains 16 repeated transmissions of the chips: 1000 0000 1010
1000. The start flag contains one transmission of eight chips: 0000 1100 0000 1100 0110 0000
0110 0000. The stop flag contains one transmission of eight chips: 0000 1100 0000 1100 0000
0110 0000 0110. The address, control, data, and CRC-32 use the standard 4PPM chip encoding to
represent two bits per chip.
11.2.3 Address Field
A transmitter uses the 8-bit address field to target a receiver when multiple stations are connected
to the same set of serial lines. The address allows up to 255 stations to be uniquely addressed (0x00
to 0xFE). The broadcast address 0xFF is used to send messages to all of the connected stations.
For reception, FICP control register 1 (ICCR1) is used to program a unique receive address. The
AME bit in the FICP control register 0 (ICCR0) determines the address match function. The
received frames’ addresses are stored in the receive FIFO with normal data.
11.2.4 Control Field
The control field is an optional 8-bit field that is defined by software. The FICP does not provide
hardware decode support for the control byte. It treats all bytes between the address and the CRC as
data.
11.2.5 Data Field
The data field can have a length from 0 to 2045 bytes. Application requirements and target
system’s transmission characteristics affect the data field’s length. Software must determine the
length of the data to maximize the amount that can be transmitted in each frame while allowing the
CRC to detect all errors during transmission. The serial port does not contain hardware that
restricts the maximum amount of data that can be transmitted or received. If a data field that is not
a multiple of eight bits is received, an abort is signalled.
Figure 11-3. Frame Format for IrDA Transmission (4.0 Mbps)
64 chips 8 chips
4 chips
(8 bits)
4 chips
(8 bits)
8180 chips
max
(2045 bytes)
16 chips
(32 bits)
8 chips
Preamble Start Flag
Address
(optional)
Control
(optional)
Data CRC-32 Stop Flag
Preamble - | 1000 | 0000 | 1010 | 1000 |... repeated at least 16 times
Start flag - | 0000 | 1100 | 0000 | 1100 | 0110 | 0000 | 0110 | 0000 |
Stop Flag - | 0000 |1100 | 0000 | 1100 | 0000 | 0110 | 0000 | 0110 |