5 mmc_cmdat register (mmc_cmdat), 5 mmc_cmdat register (mmc_cmdat) -26, Mmc_cmdat bit definitions -26 – Intel PXA255 User Manual
Page 528
15-26
Intel® PXA255 Processor Developer’s Manual
MultiMediaCard Controller
15.5.5
MMC_CMDAT Register (MMC_CMDAT)
, controls the command sequence. Writing to this register
starts the command sequence on the MMC bus when the MMC bus clock is turned on.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
0
SPI_EN
SPI Mode Enable
0 –
Disables SPI mode
1 –
Enables SPI mode
Table 15-8. MMC_SPI Bit Definitions (Sheet 2 of 2)
Physical Address
0x4110_000c
MMC_SPI Register
MultiMediaCard Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
SPI_
C
S_
AD
DR
ESS
SPI_
C
S_
EN
CR
C_
O
N
SP
I_
EN
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
Table 15-9. MMC_CMDAT Bit Definitions (Sheet 1 of 2)
Physical Address
0x4110_0010
MMC_CMDAT Register
MultiMediaCard Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
MMC
_
D
MA
_
E
N
IN
IT
BU
SY
S
T
RE
AM
_
B
L
O
C
K
W
R
IT
E
/RE
AD
DA
T
A
_
E
N
R
ESP
O
N
SE_
FO
RM
A
T
[1
:0
]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Bits
Name
Description
31:8
—
reserved
7
MMC_DMA_E
N
DMA Mode Enable
0 –
Program I/O mode
1 –
DMA mode
When DMA mode is used, this bit is a mask on RXFIFO_RD_REQ and TXFIFO_WR_REQ
interrupts.
6
INIT
80 Initialization Clocks
0 –
Do not precede command sequence with 80 clocks
1 –
Precede command sequence with 80 clocks
5
BUSY
Specifies whether a busy signal is expected after the current command.
This bit is for no data command/response transactions only.