Intel PXA255 - Manual (Page 69)

Intel® PXA255 Processor Developer’s Manual 3-7
Clocks and Power Manager
Reset, nRESET must be held low for t
DHW_NRESET
to allow the system to stabilize and the reset
state to propagate. Refer to the Intel® PXA255 Processor Electrical, Mechanical, and Thermal
Specification for details.
3.4.1.2 Behavior During Hardware Reset
During Hardware Reset, all internal registers and units are held at their defined reset conditions.
While the nRESET pin is asserted, nothing inside the processor is active except the 3.6864 MHz
oscillator. The internal clocks are stopped and the chip is static. All pins return to their reset
conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. Because the memory
controller receives a full reset, all dynamic RAM contents are lost during Hardware Reset.
3.4.1.3 Completing Hardware Reset
To complete Hardware Reset, deassert the nRESET pin. All power supplies must be stable for
t
D_NRESET
before nRESET is deasserted. Refer to the Intel® PXA255 Processor Electrical,
Mechanical, and Thermal Specification for details. After the nRESET pin is deasserted, the
following sequence occurs:
1. The 3.6864 MHz oscillator and internal PLL clock generators wait for stabilization.
2. The nRESET_OUT pin is deasserted.
3. The normal boot-up sequence begins. All processor units return to their predefined reset
conditions. Software must examine the Reset Controller Status register (RCSR) to determine
the cause for the boot.
3.4.2 Watchdog Reset
Watchdog Reset is invoked when software fails to properly prevent the Watchdog Time-out Event
from occurring. It is assumed that Watchdog Resets are only generated when software is not
executing properly and has potentially destroyed data. In Watchdog Reset all units in the are reset
except the Clocks and Power Manager.
3.4.2.1 Invoking Watchdog Reset
Watchdog Reset is invoked when the Watchdog Enable bit (WE) in the OWER is set and the
OSMR[3] matches the OS timer counter. When these conditions are met, they invoke Watchdog
Reset, regardless of the previous mode of operation. Watchdog Reset asserts nRESET_OUT.
3.4.2.2 Behavior During Watchdog Reset
During Watchdog Reset, all units except the Real Time Clock and parts of the Clocks and Power
Manager maintain their defined reset conditions. All pins except the oscillator pins assume their
reset conditions and the nBATT_FAULT and nVDD_FAULT pins are ignored. All dynamic RAM
contents are lost during Watchdog Reset because the memory controller receives a full reset.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” for the pin states during
Watchdog and other Resets.