Intel PXA255 - Manual (Page 61)

Intel® PXA255 Processor Developer’s Manual 2-31
System Architecture
0x4140_002C NSSPSP NSSP Programmable Serial Protocol
Hardware
UART
0x4160_0000
0x4160_0000 HWRBR Receive Buffer Register (read only)
0x4160_0000 HWTHR Transmit Holding Register (write only)
0x4160_0004 HWIER Interrupt Enable Register (read/write)
0x4160_0008 HWIIR Interrupt ID Register (read only)
0x4160_0008 HWFCR FIFO Control Register (write only)
0x4160_000C HWLCR Line Control Register (read/write)
0x4160_0010 HWMCR Modem Control Register (read/write)
0x4160_0014 HWLSR Line Status Register (read only)
0x4160_0018 HWMSR Modem Status Register (read only)
0x4160_001C HWSPR Scratch Pad Register (read/write)
0x4160_0020 HWISR Infrared Selection Register (read/write)
0x4160_0024 HWFOR FIFO Occupancy Register (read only)
0x4160_0028 HWABR Auto-Baud Control Register (read/write)
0x4160_002C HWACR Auto-Baud Count Register
0x4160_0000 HWDLL Divisor Latch Low Register (DLAB = 1) (read/write)
0x4160_0000 HWDLH Divisor Latch High Register (DLAB = 1) (read/write)
LCD
Controller
0x4400_0000
0x4400_0000 LCCR0 LCD Controller Control Register 0
0x4400_0004 LCCR1 LCD Controller Control Register 1
0x4400_0008 LCCR2 LCD Controller Control Register 2
0x4400_000C LCCR3 LCD Controller Control Register 3
0x4400_0200 FDADR0 DMA Channel 0 Frame Descriptor Address Register
0x4400_0204 FSADR0 DMA Channel 0 Frame Source Address Register
0x4400_0208 FIDR0 DMA Channel 0 Frame ID Register
0x4400_020C LDCMD0 DMA Channel 0 Command Register
0x4400_0210 FDADR1 DMA Channel 1 Frame Descriptor Address Register
0x4400_0214 FSADR1 DMA Channel 1 Frame Source Address Register
0x4400_0218 FIDR1 DMA Channel 1 Frame ID Register
0x4400_021C LDCMD1 DMA Channel 1 Command Register
0x4400_0020 FBR0 DMA Channel 0 Frame Branch Register
0x4400_0024 FBR1 DMA Channel 1 Frame Branch Register
0x4400_0038 LCSR LCD Controller Status Register
0x4400_003C LIIDR LCD Controller Interrupt ID Register
0x4400_0040 TRGBR TMED RGB Seed Register
0x4400_0044 TCR TMED Control Register
Memory
Controller
0x4800_0000
Table 2-8. System Architecture Register Address Summary (Sheet 11 of 12)
Unit Address Register Symbol Register Description