Intel PXA255 - Manual (Page 137)

Intel® PXA255 Processor Developer’s Manual 4-33
System Integration Unit
4.3.3.2 RTTR Value Calculations
After the true frequency of the oscillator is known, it must be divided by the desired HZ clock
frequency and this value split into integer and fractional portions. The integer portion of the value
(minus one) is loaded into the Clock Divider Count field of the RTTR. This value is compared
against a 16-bit counter clocked by the output of the oscillator multiplexor at approximately
32 kHz. When the two values are equal, the counter resets and generates a pulse which constitutes
the raw HZ clock signal.
The fractional part of the adjustment is done by periodically deleting clocks from the clock stream
driving the integer counter. The trim interval period is hardwired to be 2
10
-1 periods of the HZ
clock. If the HZ clock is programed to be 1 Hz the trim interval would be approximately 17
minutes. The number of clocks deleted (the trim delete value) is a 10-bit programmable counter
allowing from 0 to 2
10
-1 32 kHz clocks to be deleted from the input clock stream once per trim
interval. RTTR[25:16] represents the number of 32 kHz clocks deleted per trim operation.
In summary, every 2
10
-1 HZ clock periods, the integer counter stops clocking for a period equal to
the fractional error that has accumulated. If this fractional error is programmed to be zero, then no
trim operations occur and the RTC is clocked with the raw 32 kHz clock. The relationship between
the HZ clock frequency and the nominal 32 kHz clock (f1 and f32K, respectively) is shown in the
following equation.
f1 = HZ clock frequency
f32k = RTC internal clock - either the 32.678 kHz crystal output or the 3.68 MHz crystal
output divided down to 32.914 kHz
RTTR[DEL] = RTTR(25:16)
RTTR[CK_DIV] = RTTR(15:0)
4.3.3.2.1 Trim Example #1 – Measured Value Has No Fractional Component
In this example, the desired HZ clock frequency is 1 Hz. The oscillator output is measured as
36045.000 cycles/s (Hz). This output is exactly 3277 cycles over the nominal frequency of the
crystal (32.768 kHz) and has no fractional component. As such, only the integer trim function is
needed - no fractional trim is required. Accordingly, RTTR[15:0] is loaded with the binary
equivalent of 36045-1, or 0x0000_8CCC. RTTR[25:16] is left at zero (power-up state) to disable
fractional trimming. This trim exercise leaves an error of zero in trimming.
4.3.3.2.2 Trim Example #2 – Measured Value Has a Fractional Component
This example is more common in that the measured frequency of the oscillator has a fractional
component. Again, the desired HZ clock output frequency is 1 Hz. If the oscillator output is
measured as 32768.92 cycles/s (Hz), an integer trim is necessary so that the average number of
cycles counted before generating one 1 Hz clock is 32768.92. Similar to the previous example, the
integer field RTTR[15:0] is loaded with the hexadecimal equivalent of 32768-1 or 0x0000_7FFF
(reset value).
Because the actual clock frequency is 0.92 cycles per second faster than the integer value, the HZ
clock generated by just the integer trimming is slightly faster than needed and must be slowed
down. Accordingly, program the fractional trim to delete 0.92 cycles per second on average to
f1=
(2^10-1)*(RTTR[CK_DIV]+1) - RTTR[DEL]
(2^10-1)*(RTTR[CK_DIV]+1)
*
f32k
(RTTR[CK_DIV]+1)