Intel PXA255 - Manual (Page 35)

Intel® PXA255 Processor Developer’s Manual 2-5
System Architecture
2.3 I/O Ordering
The processor uses queues that accept memory requests from the three internal masters: core,
DMA Controller, and LCD Controller. Operations issued by a master are completed in the order
they were received. Operations from one master may be interrupted by operations from another
master. The processor does not provide a method to regulate the order of operations from different
masters.
Loads and stores to internal addresses are generally completed more quickly than those issued to
external addresses. The difference in completion time allows one operation to be received before
another operation, but completed after the second operation.
In the following sequence, the store to the address in r4 is completed before the store to the address
in r2 because the first store waits for memory in the queue while the second is not delayed.
str r1, [r2] ; store to external memory address [r2].
str r3, [r4] ; store to internal (on-chip) memory address [r4].
If the two stores are control operations that must be completed in order, the recommended sequence
is to insert a load to an unbuffered, uncached memory page followed by an operation that depends
on data from the load:
str r1, [r2] ; first store issued
ldr r5, [r6] ; load from external unbuffered, uncached address ([r2] if possible)
mov r5, r5 ; nop stalls until r5 is loaded
str r3, [r4] ; second store completes in program order
2.4 Semaphores
The Swap (SWP) and Swap Byte (SWPB) instructions, as described in the ARM* Architecture
reference, may be used for semaphore manipulation. No on-chip master or process can access a
memory location between the load and store portion of a SWP or SWPB to the same location.
Note: Semaphore coherency may be interrupted because an external companion chip that uses the
MBREQ/MBGNT handshake can take ownership of the bus during a locked sequence. To allow
semaphore manipulation by external companion chips, the software must manage coherency.
2.5 Interrupts
The interrupt controller is described in detail in Section 4.2, “Interrupt Controller” . All on-chip
interrupts are enabled, masked, and routed to the core FIQ or IRQ. Each interrupt is enabled or
disabled at the source through an interrupt mask bit. Generally, all interrupt bits in a unit are ORed
together and present a single value to the interrupt controller.