Intel PXA255 - Manual (Page 596)

17-26 Intel® PXA255 Processor Developer’s Manual
Hardware UART
0x4160_0008 X HWIIR “Interrupt Identification Register (IIR)” (read only)
0x4160_0008 X HWFCR “FIFO Control Register (FCR)” (write only)
0x4160_000C X HWLCR “Line Control Register (LCR)” (read/write)
0x4160_0010 X HWMCR “Modem Control Register (MCR)” (read/write)
0x4160_0014 X HWLSR “Line Status Register (LSR)” (read only)
0x4160_0018 X HWMSR “Modem Status Register (MSR)” (read only)
0x4160_001C X HWSPR “Scratchpad Register (SCR)” (read/write)
0x4160_0020 X HWISR “Infrared Selection Register (ISR)” (read/write)
0x4160_0024 X HWFOR “Receive FIFO Occupancy Register (FOR)” (read only)
0x4160_0028 X HWABR “Auto-Baud Control Register (ABR)” (read/write)
0x4160_002C X HWACR “Auto-Baud Count Register (ACR)”
0x4160_0000 1 HWDLL “Divisor Latch Registers (DLL and DLH)” low byte (read/write)
0x4160_0004 1 HWDLH “Divisor Latch Registers (DLL and DLH)” high byte (read/write)
Table 17-20. HWUART Register Locations (Sheet 2 of 2)
Register
Addresses
DLAB Bit
Value
Name Description