12 mmc_i_reg register (mmc_i_reg), 12 mmc_i_reg register (mmc_i_reg) -31 – Intel PXA255 User Manual
Page 533
Intel® PXA255 Processor Developer’s Manual
15-31
MultiMediaCard Controller
15.5.12
MMC_I_REG Register (MMC_I_REG)
MMC_I_REG, shown in
, shows the currently requested interrupt. The FIFO request
interrupts, TXFIFO_WR_REQ, and RXFIFO_RD_REQ are masked off with the MMC_DMA_EN
bit in the MMC_CMDAT register. The software is responsible for monitoring these bits in program
I/O mode.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
5
RXFIFO_RD_
REQ
Receive FIFO Read Request
0 –
Not masked
1 –
Masked
4
CLK_IS_
OFF
Clock Is Off
0 –
Not masked
1 –
Masked
3
STOP_CMD
Ready for Stop Transaction Command
0 –
Not masked
1 –
Masked
2
END_CMD_R
ES
End Command Response
0 –
Not masked
1 –
Masked
1
PRG_DONE
Programming Done
0 –
Not masked
1 –
Masked
0
DATA_TRAN_
DONE
Data Transfer Done
0 –
Not masked
1 –
Masked
Table 15-15. MMC_I_MASK Bit Definitions (Sheet 2 of 2)
Physical Address
0x4110_0028
MMC_I_MASK Register
MultiMediaCard Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
TXFIFO
_WR
_
R
E
Q
RX
F
IF
O
_
RD_
R
E
Q
CL
K
_
IS
_
O
F
F
ST
O
P
_
C
M
D
E
N
D
_
CM
D_
R
E
S
P
R
G
_
DO
NE
DA
T
A
_
T
RA
N_
DO
N
E
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Bits
Name
Description