Intel PXA255 - Manual (Page 183)

Intel® PXA255 Processor Developer’s Manual 6-1
Memory Controller
6
This chapter describes the external memory interface structures and memory-related registers
supported by the PXA255 processor.
6.1 Overview
The processor external memory bus interface supports Synchronous Dynamic Memory (SDRAM),
synchronous and asynchronous burst modes, Page-mode flash, Synchronous Mask ROM
(SMROM), Page Mode ROM, SRAM, SRAM-like Variable Latency I/O (VLIO), 16-bit PC Card
expansion memory, and Compact Flash. Memory types can be programmed through the Memory
Interface Configuration registers.
Figure 6-1 is a block diagram of the maximum configuration of
the memory controller.