1 transmit fifo service (tfs), 2 transmit packet complete (tpc), 3 flush tx fifo (ftf) – Intel PXA255 User Manual
Page 435
Intel® PXA255 Processor Developer’s Manual
12-35
USB Device Controller
12.6.8.1
Transmit FIFO Service (TFS)
The transmit FIFO service bit is set if the FIFO does not contain any data bytes and UDCCSx[TSP]
is not set.
12.6.8.2
Transmit Packet Complete (TPC)
The transmit packet complete bit is be set by the UDC when an entire packet is sent to the host.
When this bit is set, the IRx bit in the appropriate UDC status/interrupt register is set if transmit
interrupts are enabled. This bit can be used to validate the other status/error bits in the endpoint(x)
control/status register. The UDCCSx[TPC] bit is cleared by writing a 1 to it. This clears the
interrupt source for the IRx bit in the appropriate UDC status/interrupt register, but the IRx bit must
also be cleared.
The UDC issues NAK handshakes to all IN tokens if this bit is set and the buffer is not triggered by
writing 8 bytes or setting UDCCSx[TSP].
12.6.8.3
Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx FIFO bit is
set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or
SET_INTERFACE. The bit’s read value is zero.
5
FST
Force STALL (read/write).
1 = Issue STALL handshakes to IN tokens.
4
SST
Sent STALL (read/write 1 to clear).
1 = STALL handshake was sent.
3
TUR
Transmit FIFO underrun (read/write 1 to clear)
1 = Transmit FIFO experienced an underrun.
2
FTF
Flush Tx FIFO (always read 0/ write a 1 to set)
1 = Flush Contents of TX FIFO
1
TPC
Transmit packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
0
TFS
Transmit FIFO service (read-only).
0 = Transmit FIFO has no room for new data
1 = Transmit FIFO has room for 1 complete data packet
Table 12-19. UDCCS5/10/15 Bit Definitions (Sheet 2 of 2)
0x 4060_0024
0x 4060_0038
0x 4060_004C
UDCCS5
UDCCS5
UDCCS15
USB Device Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
TSP
reser
ved
FST
SST
TU
R
FTF
TP
C
TFS
Reset
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
1
Bits
Name
Description