Intel PXA255 - Manual (Page 52)

2-22 Intel® PXA255 Processor Developer’s Manual
System Architecture
0x4000_014C DRCMR19 Request to Channel Map Register for STUART receive Request
0x4000_0150 DRCMR20 Request to Channel Map Register for STUART transmit Request
0x4000_0154 DRCMR21 Request to Channel Map Register for MMC receive Request
0x4000_0158 DRCMR22 Request to Channel Map Register for MMC transmit Request
0x4000_015C DRCMR23 Reserved
0x4000_0160 DRCMR24 Reserved
0x4000_0164 DRCMR25 Request to Channel Map Register for USB endpoint 1 Request
0x4000_0168 DRCMR26 Request to Channel Map Register for USB endpoint 2 Request
0x4000_016C DRCMR27 Request to Channel Map Register for USB endpoint 3 Request
0x4000_0170 DRCMR28 Request to Channel Map Register for USB endpoint 4 Request
0x4000_0174 DRCMR29 Request to Channel Map Register for HWUART receive Request
0x4000_0178 DRCMR30 Request to Channel Map Register for USB endpoint 6 Request
0x4000_017C DRCMR31 Request to Channel Map Register for USB endpoint 7 Request
0x4000_0180 DRCMR32 Request to Channel Map Register for USB endpoint 8 Request
0x4000_0184 DRCMR33 Request to Channel Map Register for USB endpoint 9 Request
0x4000_0188 DRCMR34 Request to Channel Map Register for HWUART transmit Request
0x4000_018C DRCMR35 Request to Channel Map Register for USB endpoint 11 Request
0x4000_0190 DRCMR36 Request to Channel Map Register for USB endpoint 12 Request
0x4000_0194 DRCMR37 Request to Channel Map Register for USB endpoint 13 Request
0x4000_0198 DRCMR38 Request to Channel Map Register for USB endpoint 14 Request
0x4000_019C DRCMR39 Reserved
0x4000_0200 DDADR0 DMA Descriptor Address Register Channel 0
0x4000_0204 DSADR0 DMA Source Address Register Channel 0
0x4000_0208 DTADR0 DMA Target Address Register Channel 0
0x4000_020C DCMD0 DMA Command Address Register Channel 0
0x4000_0210 DDADR1 DMA Descriptor Address Register Channel 1
0x4000_0214 DSADR1 DMA Source Address Register Channel 1
0x4000_0218 DTADR1 DMA Target Address Register Channel 1
0x4000_021C DCMD1 DMA Command Address Register Channel 1
0x4000_0220 DDADR2 DMA Descriptor Address Register Channel 2
0x4000_0224 DSADR2 DMA Source Address Register Channel 2
0x4000_0228 DTADR2 DMA Target Address Register Channel 2
0x4000_022C DCMD2 DMA Command Address Register Channel 2
0x4000_0230 DDADR3 DMA Descriptor Address Register Channel 3
0x4000_0234 DSADR3 DMA Source Address Register Channel 3
0x4000_0238 DTADR3 DMA Target Address Register Channel 3
0x4000_023C DCMD3 DMA Command Address Register Channel 3
0x4000_0240 DDADR4 DMA Descriptor Address Register Channel 4
0x4000_0244 DSADR4 DMA Source Address Register Channel 4
0x4000_0248 DTADR4 DMA Target Address Register Channel 4
Table 2-8. System Architecture Register Address Summary (Sheet 2 of 12)
Unit Address Register Symbol Register Description