Intel PXA255 - Manual (Page 502)

14-16 Intel® PXA255 Processor Developer’s Manual
Inter-Integrated-Circuit Sound (I2S) Controller
Table 14-12. Register Memory Map
Address
(paddr(9:0) Register
name
Description
0x4040_0000 SACR0 Global Control Register
0x4040_0004 SACR1 Serial Audio I 2 S/MSB-Justified Control Register
0x4040_0008 — reserved
0x4040_000C SASR0 Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register
0x4040_0014 SAIMR Serial Audio Interrupt Mask Register
0x4040_0018 SAICR Serial Audio Interrupt Clear Register
0x4040_001C
through
0x4040_005C
— reserved
0x4040_0060 SADIV Audio clock divider register. See Section 14.4 .
0x4040_0064
through
0x4040_007C
— reserved
0x4040_0080 SADR Serial Audio Data Register (TX and RX FIFO access register).