Intel PXA255 - Manual (Page 430)

12-30 Intel® PXA255 Processor Developer’s Manual
USB Device Controller
exception is RNE which will get set with RPC but will clear itself once the active FIFO is empty.
After clearing RPC, the next buffer will become active and the status bits will be updated
accordingly, including RPC. The UDCCSx[RPC] bit is cleared by writing a 1 to it. The UDC issues
NAK handshakes to all OUT tokens while this bit is set and both buffers have unread data.
12.6.5.3 Bit 2 Reserved
Bit 2 is reserved for future use.
12.6.5.4 DMA Enable (DME)
The dma enable is used by the UDC to control the timing of the data received interrupt. If the bit is
set, the interrupt is asserted if the end of packet has been received and the receive FIFO has less
than 32 bytes of data remaining in it. If the bit is not set, the interrupt is asserted when the end of
packet is received and all of the received data is still in the receive FIFO.
12.6.5.5 Sent Stall (SST)
The sent stall bit is set by the UDC in response to FST successfully forcing a user induced STALL
on the USB bus. This bit is not set if the UDC detects a protocol violation from the host PC when a
STALL handshake is returned automatically. In either event, the core does not intervene and the
UDC clears the STALL status when the host sends a CLEAR_FEATURE command. Any valid
data in the FIFO remains valid and the software must unload it. The endpoint operation continues
normally and does not send another STALL condition, even if the UDCCSx[SST] bit is set. To
allow the software to continue to send the STALL condition on the USB bus, the UDCCSx[FST]
bit must be set again. The core writes a 1 to the sent stall bit to clear it.
12.6.5.6 Force Stall (FST)
The core can set the force stall bit to force the UDC to issue a STALL handshake to all OUT
tokens. STALL handshakes continue to be sent until the core clears this bit by sending a Clear
Feature command. The UDCCSx[SST] bit is set when the STALL state is actually entered, but this
may be delayed if the UDC is active when the UDCCSx[FST] bit is set. The UDCCSx[FST] bit is
automatically cleared when the UDCCSx[SST] bit is set. To ensure that no data is transmitted after
the Clear Feature command is sent and the host resumes IN requests, software must clear the
transmit FIFO by setting the UDCCSx[FTF] bit.
12.6.5.7 Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that unread data remains in the receive FIFO. This bit
must be polled when the UDCCSx[RPC] bit is set to determine if there is any data in the FIFO that
the DMA did not read. The receive FIFO must continue to be read until this bit clears or data will
be lost.
12.6.5.8 Receive Short Packet (RSP)
The UDC uses the receive short packet bit to indicate that the received OUT packet in the active
buffer currently being read is a short packet or zero-sized packet. This bit is updated by the UDC
after the last byte is read from the active buffer and reflects the status of the new active buffer. If
UDCCSx[RSP] is a one and UDCCSx[RNE] is a 0, it indicates a zero-length packet. If a zero-
length packet is present, the core must not read the data register. UDCCSx[RSP] is cleared when
the next OUT packet is received.