Intel PXA255 - Manual (Page 321)

Intel® PXA255 Processor Developer’s Manual 8-13
Synchronous Serial Port Controller
Note: Loop back mode cannot be used with Microwire frame format.
8.7.2.4 Serial Clock Polarity (SPO)
The serial clock polarity bit (SPO) selects the SSPSCLK signal’s inactive state in the Motorola SPI
format (FRF=00). For SPO=0, the SSPSCLK is held low in the inactive or idle state when the SSP
is not transmitting/receiving data. When the SPO bit is set to a 1, the SSPSCLK is held high during
the inactive/idle state. The SPO bit’s programmed setting alone does not determine which
SSPSCLK edge is used to transmit or receive data. The SPO bit’s setting combined with the
SSPSCLK phase bit (SPH) determine which edge is used.
Note: The SPO bit is ignored for all data frame formats except for the Motorola SPI format (FRF=00).
8.7.2.5 Serial Clock Phase (SPH)
The serial clock (SSPSCLK) phase bit (SPH) determines the phase relationship between the
SSPSCLK and the serial frame (SSPSFRM) pins for the Motorola SPI format (FRF=00). When
SPH=0, SSPSCLK remains in its inactive/idle state (as determined by the SPO setting) for one full
cycle after SSPSFRM is asserted low at the beginning of a frame. SSPSCLK continues to transition
for the rest of the frame and is then held in its inactive state for one-half of an SSPSCLK period
before SSPSFRM is deasserted high at the end of the frame. When SPH=1, SSPSCLK remains in
its inactive/idle state (as determined by the SPO setting) for one-half cycle after SSPSFRM is
asserted low at the beginning of a frame. SSPSCLK continues to transition for the rest of the frame
and is then held in its inactive state for one full SSPSCLK period before SSPSFRM is deasserted
high at the end of the frame.
The combination of the SPO and SPH settings determines when SSPSCLK is active during the
assertion of SSPSFRM and which SSPSCLK edge is used to transmit and receive data on the
SSPTXD and SSPRXD pins. When SPO and SPH are programmed to the same value, transmit data
is driven on SSPSCLK’s falling edge and receive data is latched on SSPSCLK’s rising edge. When
SPO and SPH are programmed to opposite values (one 0 and the other 1), transmit data is driven on
SSPSCLK’s rising edge and receive data is latched on SSPSCLK’s falling edge.
The SPH is ignored for all data frame formats except the Motorola SPI format (FRF=00).
Figure 8-4 shows the pin timing for the four SPO and SPH programming combinations. SPO
inverts the SSPSCLK signal’s polarity and SPH determines the phase relationship between
SSPSCLK and SSPSFRM, shifting the SSPSCLK signal one-half phase to the left or right during
the SSPSFRM assertion.
Figure 8-4. Motorola SPI* Frame Formats for SPO and SPH Programming
SSPSCLK SPO=0
...
SSPSCLK SPO=1
...
SSPSFRM
...
SSPTXD Bit<N> Bit<N-1 > ... Bit<1> Bit<0>