Intel PXA255 - Manual (Page 324)

8-16 Intel® PXA255 Processor Developer’s Manual
Synchronous Serial Port Controller
8.7.4 SSP Status Register (SSSR)
The SSP Status Register (SSSR) is shown in Table 8-6 . The SSSR contains bits that signal overrun
errors and transmit and receive FIFO service requests. These hardware-detected events signal an
interrupt request to the interrupt controller. The status register also contains flags that indicate
when the SSP is actively transmitting or receiving characters, when the transmit FIFO is not full,
and when the receive FIFO is not empty (no interrupt generated).
Bits that cause an interrupt will signal the request as long as the bit is set. When the bit is cleared,
the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags. Status
bits are referred to as sticky (once set by hardware, they must be cleared by software). Writing a 1
to a sticky status bit clears it. Writing a 0 has no effect. Read-only flags are set and cleared by
hardware. Writes have no effect. Some bits that cause interrupts have corresponding mask bits in
the control registers.
All bits are read-only except ROR, which is read/write. ROR’s reset state is zero. Writes to TNF,
RNE, BSY, TFS, and RFS have no effect. Writes to reserved bits are ignored and reads from these
bits are undetermined.