4 interrupt enable register (ier), Dll bit definitions -8, Dlh bit definitions -8 – Intel PXA255 User Manual
Page 364: Table 10-5, Table 10-6
10-8
Intel® PXA255 Processor Developer’s Manual
UARTs
10.4.2.4
Interrupt Enable Register (IER)
The IER, shown in
, enables the five types of interrupts that set a value in the Interrupt
Identification Register (IIR). To disable an interrupt, software must clear the appropriate bit in the
IER. Software can enable some interrupts by setting the appropriate bit.
The Character Timeout Indication interrupt is separated from the Received Data Available interrupt
to ensure that the processor and the DMA controller do not service the receive FIFO at the same
time. When a Character Timeout Indication interrupt occurs, the processor must handle the data in
the Receive FIFO through programmed I/O.
An error interrupt is used when DMA requests are enabled. The interrupt is generated when LSR
bit 7 is set to a 1, because a receive DMA request is not generated when the receive FIFO has an
error. The error interrupt tells the processor to handle the data in the receive FIFO through
programmed I/O. The error interrupt is enabled when DMA requests are enabled and it can not be
masked. Receiver Line Status interrupts occur when the error is at the front of the FIFO.
Note:
When DMA requests are enabled and an interrupt occurs, software must first read the LSR to see if
an error interrupt exists, then check the IIR for the source of the interrupt. When the last error byte
is read from the FIFO, DMA requests are automatically enabled. Software is not required to check
for the error interrupt if DMA requests are disabled because an error interrupt only occurs when
DMA requests are enabled.
Table 10-5. DLL Bit Definitions
Base (DLAB=1)
Divisor Latch Low Register
UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
DL
L
7
DL
L
6
DL
L
5
DL
L
4
DL
L
3
DL
L
2
DL
L
1
DL
L
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:8
—
reserved
7:0
DLL[7:0]
Low byte compare value to generate baud rate.
Table 10-6. DLH Bit Definitions
Base+0x04 (DLAB=1)
Divisor Latch High Register
UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
DL
H
1
5
DL
H
1
4
DL
H
1
3
DL
H
1
2
DL
H
1
1
DL
H
1
0
DL
H
9
DL
H
8
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:8
—
reserved
7:0
DLH[7:0]
High byte compare value to generate baud rate.