1 gpio pin-level registers (gplr0, gplr1, gplr2), Gplr0 bit definitions -7 – Intel PXA255 User Manual
Page 111
Intel® PXA255 Processor Developer’s Manual
4-7
System Integration Unit
Note:
GPLR2[31:17], GPSR2[31:17], GPCR2[31:17], GPDR2[31:17], GRER2[31:17], GFER2[31:17],
GEDR2[31:17] and GAFR2_U[31:2] are reserved bits. Write zeros to these bits and ignore all
reads from these bits.
Note:
All GPIO registers are initialized to 0x0 at reset, which results in all GPIO pins being initialized as
inputs.
4.1.3.1
GPIO Pin-Level Registers (GPLR0, GPLR1, GPLR2)
Check the state of each of the GPIO pins by reading the GPIO Pin Level register (GPLR). Each bit
in the GPLR corresponds to one pin in the GPIO. GPLR0[31:0] correspond to GPIO[31:0],
GPLR1[31:0] correspond to GPIO[63:32] and GPLR2[16:0] correspond to GPIO[80:64]. Use the
GPLR0
–
2 read-only registers to determine the current value of a particular pin (regardless of the
programmed pin direction). For reserved bits (GPLR2[31:17]), reads return zero.
This is read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
GRER
Detect Rising/Falling
Edge
GRER0
GRER1
GRER2
GFER
GFER0
GFER1
GFER2
GEDR
Detect Edge Type
GEDR0
GEDR1
GEDR2
GAFR
Set Alternate Functions
GAFR0_L
GAFR0_U
GAFR1_L
GAFR1_U
GAFR2_L
GAFR2_U
NOTE: For the alternate function registers, the designator _L signifies that the lower 16 GPIOs’ alternate functions are configured
by that register and _U designates that the upper 16 GPIOs’ alternate functions are configured by that register.
Table 4-2. GPIO Register Definitions (Sheet 2 of 2)
Register
Type
Register Function
GPIO[15:0]
GPIO[31:16]
GPIO[47:32]
GPIO[63:48]
GPIO[79:64]
GPIO[80]
Table 4-3. GPLR0 Bit Definitions
Physical Address
0x40E0_0000
GPLR0
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PL
3
1
PL
3
0
PL
2
9
PL
2
8
PL
2
7
PL
2
6
PL
2
5
PL
2
4
PL
2
3
PL
2
2
PL
2
1
PL
2
0
PL
1
9
PL
1
8
PL
1
7
PL
1
6
PL
1
5
PL
1
4
PL
1
3
PL
1
2
PL1
1
PL
1
0
PL
9
PL
8
PL
7
PL
6
PL
5
PL
4
PL
3
PL
2
PL
1
PL
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
<31:0>
PL[x]
GPIO Pin Level ‘x’ (where x = 0 to 31).
This read-only field indicates the current value of each GPIO.
0 – Pin state is low
1 – Pin state is high