Uicr0 bit definitions -37 – Intel PXA255 User Manual
Page 437
Intel® PXA255 Processor Developer’s Manual
12-37
USB Device Controller
12.6.9.1
Interrupt Mask Endpoint x (IMx), Where x is 0 through 7
The UICR0[IMx] bit is used to mask or enable the corresponding endpoint interrupt request,
USIR0[IRx]. When the mask bit is set, the interrupt is masked and the corresponding bit in the
USIR0 register is not allowed to be set. When the mask bit is cleared and an interruptible condition
occurs in the endpoint, the appropriate interrupt bit is set. Programming the mask bit to a 1 does not
affect the current state of the interrupt bit. It only blocks future zero to one transitions of the
interrupt bit.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 12-20. UICR0 Bit Definitions
0x 4060_0050
UICR0
USB Device Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
IM
7
IM
6
IM
5
IM
4
IM
3
IM
2
IM
1
IM
0
Reset
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
1
1
1
1
Bits
Name
Description
31:8
—
reserved
7
IM7
Interrupt Mask for Endpoint 7
0 = Receive interrupt enabled
1 = Receive interrupt disabled
6
IM6
Interrupt Mask for Endpoint 6
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
5
IM5
Interrupt mask for Endpoint 5
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
4
IM4
Interrupt mask for Endpoint 4
0 = Receive Interrupt enabled
1 = Receive Interrupt disabled
3
IM3
Interrupt mask for Endpoint 3
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
2
IM2
Interrupt Mask for Endpoint 2
0 = Receive interrupt enabled
1 = Receive interrupt disabled
1
IM1
Interrupt Mask for Endpoint 1
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
0
IM0
Interrupt mask for endpoint 0
0 = Endpoint zero interrupt enabled
1 = Endpoint zero interrupt disabled