Intel PXA255 - Manual (Page 211)

Intel® PXA255 Processor Developer’s Manual 6-29
Memory Controller
Figure 6-5. Basic SDRAM Timing Parameters
Figure 6-6. SDRAM_Read_diffbank_diffrow
CL CL tRCD tRCD tRP tRP
bank row col
0 1 2 3
tRP = 2 clks
tRAS = 2 clks
tRCD = 2 clks
CL = 2 clks
0000
0ns 50ns 100ns 150ns 200ns
SDCLK
nSDCS
MA[24:0]
nSDRAS
nSDCAS
nWE
DATA
DQM[3:0]
CL CL tRCD tRCD
tRP
CL
tRP
CL tRCD tRCD
row col
0 1 2 3
0000
tRP = 2 clks
tRAS = 7 clks
tRCD = 2 clks
CL = 2 clks
bank0 row
1 2 3 4
col
0ns 25ns 50ns 75ns 100ns 125ns
SDCLK
nSDCS
MA[24:0]
nSDRAS
nSDCAS
nWE
DATA
DQM[3:0]