Intel PXA255 - Manual (Page 232)

6-50 Intel® PXA255 Processor Developer’s Manual
Memory Controller
Figure 6-18. Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash (MSC0[RDF] = 4,
MSC0[RDN] = 1, MSC0[RRR] = 0)
0 1 2 3 4 5 6 7
"00"
"0000"
tDOH
tDSOH
tCEH tCES
RRR*2+1 RDF+1
RDN+1 RDF+2 RDN+1 RDF+2
tAS
tAS = Address Setup to nCS asserted = 1 clk_mem
tCES = nCS setup to nOE asserted = 0 ns
tCEH = nCS hold from nOE deasserted = 0 ns
tDSOH = MD setup to Address changing = 1.5 clk_mems plus
board routing delays
tDOH = MD hold from Address changing = 0 ns * MSC0:RDF0 = 4, RDN0 = 1, RRR0 = 1
0ns 50ns 100ns 150ns 200ns 250ns
CLK_MEM
nCS[0]
MA[25:5]
MA[4:2]
MA[1:0]
nADV(nSDCAS)
nOE
nWE
RDnWR
MD[31:0]
DQM[3:0]
nCS[1]