1 receive fifo service (rfs), 2 receive packet complete (rpc), Udccs2/7/12 bit definitions -29 – Intel PXA255 User Manual
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Intel® PXA255 Processor Developer’s Manual
12-29
USB Device Controller
12.6.5
UDC Endpoint x Control/Status Register (UDCCS2/7/12)
UDCCS2/7/12, shown in
, contains 7 bits that are used to operate endpoint x, a Bulk
OUT endpoint.
12.6.5.1
Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it and the
packet has been error checked by the UDC. A complete packet may be 64 bytes, a short packet, or
a zero packet. This bit is not cleared until all data has been read from both buffers.
12.6.5.2
Receive Packet Complete (RPC)
The receive packet complete bit is set by the UDC when an OUT packet is received. When this bit
is set, the IRx bit in the appropriate UDC status/interrupt register is set, if receive interrupts are
enabled. This bit must be used to validate the other status/error bits in the endpoint(x) control/status
register. Status bits are not updated until RPC is set. Status bits stay set until RPC is cleared. The
Table 12-16. UDCCS2/7/12 Bit Definitions
0x 4060_0018
0x 4060_002C
0x 4060_0040
UDCCS2
UDCCS7
UDCCS12
USB Device Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
RSP
RN
E
FST
SST
DM
E
reser
ved
RP
C
RF
S
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
Bit
Name
Description
31:8
—
reserved
7
RSP
Receive short packet (read-only).
1 = Short packet received and ready for reading.
6
RNE
Receive FIFO not empty (read-only).
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
5
FST
Force stall (read/write).
1 = Issue STALL handshakes to OUT tokens.
4
SST
Sent stall (read/write 1 to clear).
1 = STALL handshake was sent.
3
DME
DMA Enable(read/write)
0 = Send data received interrupt after EOP received
1 = Send data received interrupt after EOP received and Receive FIFO has < 32 bytes of
data
2
—
reserved
1
RPC
Receive packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
0
RFS
Receive FIFO service (read-only).
0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.