4 mmc_spi register (mmc_spi), 4 mmc_spi register (mmc_spi) -25, Mmc_clk bit definitions -25 – Intel PXA255 User Manual
Page 527: Mmc_spi bit definitions -25
Intel® PXA255 Processor Developer’s Manual
15-25
MultiMediaCard Controller
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
15.5.4
MMC_SPI Register (MMC_SPI)
, is for SPI mode only and is set by the software.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-7. MMC_CLK Bit Definitions
Physical Address
0x4110_0008
MMC_CLKRT Register
MultiMediaCard Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
CLK_RAT
E[2:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:3
—
reserved
2:0
CLK_RATE[2:
0]
000 – 20 MHz clock
001 – 10 MHz clock, 1/2 of 20 MHz clock
010 – 5 MHz clock, 1/4 of 20 MHz clock
011 – 2.5 MHz clock, 1/8 of 20MHz clock
100 – 1.25MHz clock, 1/16 of 20 MHz clock
101 – 0.625 MHz clock, 1/32 of 20 MHz clock
110 – 0.3125 MHz clock, 1/64 of 20 MHz clock
111 – reserved
Table 15-8. MMC_SPI Bit Definitions (Sheet 1 of 2)
Physical Address
0x4110_000c
MMC_SPI Register
MultiMediaCard Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
SP
I_
C
S
_
A
DD
RES
S
SP
I_
C
S
_
E
N
CR
C_
O
N
SP
I_
E
N
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:4
—
reserved
3
SPI_CS_ADD
RESS
Specifies the relative address of the card to activate the SPI CS
0 –
Enables CS1
1 –
Enables CS0
2
SPI_CS_EN
SPI Chip Select Enable
0 –
Disables the SPI chip select
1 –
Enables the SPI chip select
1
CRC_ON
CRC Generation Enable
0 –
Disables CRC generation and verification
1 –
Enables CRC generation and verification