Intel PXA255 - Manual (Page 188)

6-6 Intel® PXA255 Processor Developer’s Manual
Memory Controller
Figure 6-3 shows an alternate memory configuration. This system uses 2M x 16 SMROM devices
in static banks 0 and 1, and RAM devices in static bank 2.
Figure 6-3. Static Memory System Example
2Mx16
SMROM
nCS
nRAS
nCAS
CLK
CKE
nMR
addr(12:0)
DQML
DQMH
DQ(15:0)
2Mx16
SMROM
nCS
nRAS
nCAS
CLK
CKE
nMR
addr(12:0)
DQML
DQMH
DQ(15:0)
SRAM
nCS
nOE
nWE
addr(20:0)
DQML
DQMH
DQ(15:0)
2Mx16
SMROM
nCS
nRAS
nCAS
CLK
CKE
nMR
addr(12:0)
DQML
DQMH
DQ(15:0)
2Mx16
SMROM
nCS
nRAS
nCAS
CLK
CKE
nMR
addr(12:0)
DQML
DQMH
DQ(15:0)
SRAM
nCS
nOE
nWE
addr(20:0)
DQML
DQMH
DQ(15:0)
MD(31:0)
nOE
MA(22:2)
SDCLK(0)
nSDRAS, nSDCAS, nWE, CKE(0)
nCS(2:0)
0
0
1
1
2
2
15:0
31:16
DQM[3:0]
31:16 31:16
3
2
1
0
15:0 15:0
22:10 22:10
22:10 22:10
22:2
22:2
0 0
1 1
2 2
3 3