Intel PXA255 - Manual (Page 262)

6-80 Intel® PXA255 Processor Developer’s Manual
Memory Controller
0x4800_003C MCIO1 Card interface I/O Space Socket 1 Timing Configuration
0x4800_0040 MDMRS MRS value to be written to SDRAM
0x4800_0044 BOOT_DEF
Read-Only Boot-time register. Contains BOOT_SEL and
PKG_SEL values.
0x4800 0058 MDMRSLP
Low-Power SDRAM Mode Register Set Configuration
Register
Table 6-40. Memory Controller Register Summary (Sheet 2 of 2)
Physical Address Symbol Register Name