Intel PXA255 - Manual (Page 256)

6-74 Intel® PXA255 Processor Developer’s Manual
Memory Controller
6.10.2.2 Boot-Time Configurations
The boot time configurations are shown in Figure 6-33 - Figure 6-35 . A boot from a single 32-Mbit
SMROM with nWORD = 1 is not supported.
Three Configuration registers are affected at reset - MSC0:RBW0, MDREFR:E0PIN/K0RUN, and
SXCNFG.
Figure 6-33. Asynchronous Boot Time Configurations and Register Defaults
BOOT_SEL[2:0] = 000
Asynchronous
32-bit
ROM
32
MSC0
SXCNFG
0x7FF0_7FF0
0x0004_0004
RBW0 = 0
BOOT_SEL[2:0] = 001
Asynchronous
16-bit
ROM
16
MSC0
SXCNFG
0x7FF0_7FF8
0x0004_0004
RBW0 = 1
MDREFR 0x03CA_4FFF
E0PIN = 0, K0RUN = 0
MDREFR 0x03CA_4FFF
E0PIN = 0, K0RUN = 0
BOOT_SEL[2:0] = 000
BOOT_SEL[2:0] = 000
SXMRS
SXMRS
0000_0000
0000_0000