11 reset controller status register (rcsr), 11 reset controller status register (rcsr) -33, Pgsr2 bit definitions -33 – Intel PXA255 User Manual
Page 95: Table 3-18
Intel® PXA255 Processor Developer’s Manual
3-33
Clocks and Power Manager
3.5.11
Reset Controller Status Register (RCSR)
The CPU uses the RCSR, shown in
, to determine a reset’s last cause or causes. The
processor can be reset in four ways:
•
Hardware reset
•
Watchdog reset
•
Sleep mode
•
GPIO reset
Refer to
Table 2-4, “Effect of Each Type of Reset on Internal Register State” on page 2-6
for details
of the behavior of different modules during each type of reset.
Each RCSR status bit is set by a different reset source and can be cleared by writing a 1 back to the
bit. The RCSR status bits for watchdog reset, sleep mode, and GPIO resets have a hardware reset
state of zero.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-18. PGSR2 Bit Definitions
0x40F0_0028
PGSR2
Clocks and Power Manager
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
SS
8
4
SS
8
3
SS
8
2
SS
8
1
SS
8
0
SS
7
9
SS
7
8
SS
7
7
SS
7
6
SS
7
5
SS
7
4
SS
7
3
SS
7
2
SS
7
1
SS
7
0
SS
6
9
SS
6
8
SS
6
7
SS
6
6
SS
6
5
SS
6
4
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
[31:17]
—
reserved
[16:0]
SSx
If programmed as an output, Sleep state of GPx
0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.