Intel PXA255 - Manual (Page 119)

Intel® PXA255 Processor Developer’s Manual 4-15
System Integration Unit
4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)
GEDR0, GEDR1, GEDR2, shown in Table 4-21 , Table 4-22 , and Table 4-23 , contain a total of 81
status bits that correspond to the 81 GPIO pins. When an edge detect occurs on a pin that matches
the type of edge programmed in the GRER and/or GFER registers, the corresponding status bit is
set in GEDR. Once a GEDR bit is set by an edge event, the bit remains set until the user clears it by
writing a one to the status bit. Writing a zero to a GEDR status bit has no effect.
Each edge detect that sets the corresponding GEDR status bit for GPIO[80:0] can trigger an
interrupt request. GPIO[80:2] together form a group that can cause one interrupt request to be
triggered when any one of GEDR[80:2] are set. GPIO[0] and GPIO[1] cause independent first-
level interrupts. Refer to
Section 4.2 , for a description of the programming of GPIO interrupts.
Table 4-21 through Table 4-23 show the bitmaps of the GEDR0, GEDR1, and GEDR2.
Table 4-21. GEDR0 Bit Definitions
Physical Address
0x40E0_0048
GEDR0 System Integration Unit
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED
3
1
ED
3
0
ED
2
9
ED
2
8
ED
2
7
ED
2
6
ED
2
5
ED
2
4
ED
2
3
ED
2
2
ED
2
1
ED
2
0
ED
1
9
ED
1
8
ED
1
7
ED
1
6
ED
1
5
ED
1
4
ED
1
3
ED
1
2
ED
1
1
ED
1
0
ED
9
ED
8
ED
7
ED
6
ED
5
ED
4
ED
3
ED
2
ED
1
ED
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> ED[x]
GPIO Pin ‘x’ Edge Detect Status (where x= 0 through 31).
READ
0 – No edge detect has occurred on pin as specified in GRER and/or GFER.
1 – Edge detect has occurred on pin as specified in GRER and/or GFER.
WRITE
0 – No effect.
1 – Clear edge detect status field.
Table 4-22. GEDR1 Bit Definitions
Physical Address
0x40E0_004C
GEDR1 System Integration Unit
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED6
3
ED6
2
ED6
1
ED6
0
ED5
9
ED5
8
ED5
7
ED5
6
ED5
5
ED5
4
ED5
3
ED5
2
ED5
1
ED5
0
ED4
9
ED4
8
ED4
7
ED4
6
ED4
5
ED4
4
ED4
3
ED4
2
ED4
1
ED4
0
ED3
9
ED3
8
ED3
7
ED3
6
ED3
5
ED3
4
ED3
3
ED3
2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:0> ED[x]
GPIO Pin ‘x’ Edge Detect Status (where x= 32 through 63).
READ
0 – No edge detect has occurred on pin as specified in GRER and/or GFER.
1 – Edge detect has occurred on pin as specified in GRER and/or GFER.
WRITE
0 – No effect.
1 – Clear edge detect status field.