6 ficp status register 1 (icsr1), 6 ficp status register 1 (icsr1) -15, Icsr1 bit definitions -15 – Intel PXA255 User Manual
Page 399
Intel® PXA255 Processor Developer’s Manual
11-15
Fast Infrared Communication Port
11.3.6
FICP Status Register 1 (ICSR1)
ICSR1, shown in
, contains flags that indicate that the receiver is synchronized, the
transmitter is active, the transmit FIFO is not full, the receive FIFO is not empty, and that an EOF,
CRE, or underrun error has occurred.
This is a read-only register. Ignore reads from reserved bits.
.
Table 11-7. ICSR1 Bit Definitions
0x4080_0018
Fast Infrared Communication Port
Status Register 1 (ICSR1)
Fast Infrared Communication Port
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
ROR
CR
E
EO
F
TN
F
RN
E
TBY
RSY
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Bits
Name
Description
[31:7]
—
reserved
6
ROR
Receive FIFO overrun (read-only).
0 = Receive FIFO has not experienced an overrun.
1 = Receive logic attempted to place data into receive FIFO while it was full. Data received
after the FIFO is full are lost.
Each time an 11-bit value reaches the bottom of the receive FIFO, bit 10 from the last FIFO
entry is transferred to the ROR bit.
5
CRE
CRC error (read-only).
0 = CRC not encountered yet or no CRC check errors encountered in the receipt of data.
1 = CRC calculated on the incoming data. Does not match CRC value contained within
the received frame.
Each time an 11-bit value reaches the bottom of the receive FIFO, bit 9 from the last FIFO
entry is transferred to the CRE bit.
4
EOF
End of frame (read-only).
0 = Current frame has not completed.
1 = The value at the bottom of the receive FIFO is the last byte of data within the frame,
including aborted frames.
Each time an 11-bit value reaches the bottom of the receive FIFO, bit 8 from the last FIFO
entry is transferred to the EOF bit.
3
TNF
Transmit FIFO not full (read-only).
0 = Transmit FIFO is full.
1 = Transmit FIFO is not full (no interrupt generated).
2
RNE
Receive FIFO not empty (read-only).
0 = Receive FIFO is empty.
1 = Receive FIFO is not empty (no interrupt generated).
1
TBY
Transmitter busy flag (read-only).
0 = Transmitter is idle (continuous preambles) or disabled.
1 = Transmit logic is currently transmitting a frame (address, control, data, CRC, or start/
stop flag). No interrupt generated.
0
RSY
Receiver synchronized flag (read-only).
0 = Receiver is in hunt mode or is disabled.
1 = Receiver logic is synchronized with the incoming data (no interrupt generated).