Intel PXA255 - Manual (Page 247)

Intel® PXA255 Processor Developer’s Manual 6-65
Memory Controller
Figure 6-28 shows the glue logic need for a 2-socket system. RDY/nBSY signals are routed
through a buffer to two separate GPIO pins. In the data bus transceiver control logic, nPCE1
controls the enable for the low byte lane and nPCE2 controls the enable for the high byte lane.\
Figure 6-27. Expansion Card External Logic for a One-Socket Configuration
MD<15:0> D<15:0>
nOE DIR
nCD<1>
nCD<2>
RDY/nBSY
A[25:0]
nREG
nCE<2:1>
nOE
nWE
nIOR
nIOW
nWAIT
nIOIS16
GPIO<w>
GPIO<x>
MA[25:0]
nPREG
nPOE
nPWE
nPIOR
nPIOW
nPWAIT
nIOIS16
nPCE<2:1>
GPIO<y>
PSKTSEL
RD/nWR
GPIO<z>
Intel® - PXA255 Processor
Socket 0
nPCD0
nPCD1
PRDY_BSY0
PADDR_EN0
5V to 3.3V or 2.5V
5V to 3.3V or 2.5V