3 os timer watchdog match enable register (ower), 4 os timer count register (oscr), 5 os timer status register (ossr) – Intel PXA255 User Manual

3 os timer watchdog match enable register (ower), 4 os timer count register (oscr), 5 os timer status register (ossr) | Ower bit definitions -37, Oscr bit definitions -37 | Intel PXA255 User Manual | Page 141 / 598