3 dmac registers, 1 dma interrupt register (dint), 2 dma channel control/status register (dcsrx) – Intel PXA255 User Manual

Page 167: Dmac registers -17 5.3.1, Dma interrupt register (dint) -17, Dma channel control/status register (dcsrx) -17, Dint bit definitions -17, N in, Table 5-6, Section 5.3.1

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3 dmac registers, 1 dma interrupt register (dint), 2 dma channel control/status register (dcsrx) | Dmac registers -17 5.3.1, Dma interrupt register (dint) -17, Dma channel control/status register (dcsrx) -17, Dint bit definitions -17, N in, Table 5-6, Section 5.3.1 | Intel PXA255 User Manual | Page 167 / 598 3 dmac registers, 1 dma interrupt register (dint), 2 dma channel control/status register (dcsrx) | Dmac registers -17 5.3.1, Dma interrupt register (dint) -17, Dma channel control/status register (dcsrx) -17, Dint bit definitions -17, N in, Table 5-6, Section 5.3.1 | Intel PXA255 User Manual | Page 167 / 598
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