3 udc endpoint 0 control/status register (udccs0), 1 out packet ready (opr), 2 in packet ready (ipr) – Intel PXA255 User Manual

Page 425: Udccs0 bit definitions -25

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3 udc endpoint 0 control/status register (udccs0), 1 out packet ready (opr), 2 in packet ready (ipr) | Udccs0 bit definitions -25 | Intel PXA255 User Manual | Page 425 / 598 3 udc endpoint 0 control/status register (udccs0), 1 out packet ready (opr), 2 in packet ready (ipr) | Udccs0 bit definitions -25 | Intel PXA255 User Manual | Page 425 / 598
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