12 udc status/interrupt register 1 (usir1), 1 endpoint 8 interrupt request (ir8), 2 endpoint 9 interrupt request (ir9) – Intel PXA255 User Manual

Page 441: 3 endpoint 10 interrupt request (ir10), 12 udc status/interrupt register 1 (usir1) -41, Usir1 bit definitions -41, Table 12-23

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12 udc status/interrupt register 1 (usir1), 1 endpoint 8 interrupt request (ir8), 2 endpoint 9 interrupt request (ir9) | 3 endpoint 10 interrupt request (ir10), 12 udc status/interrupt register 1 (usir1) -41, Usir1 bit definitions -41, Table 12-23 | Intel PXA255 User Manual | Page 441 / 598 12 udc status/interrupt register 1 (usir1), 1 endpoint 8 interrupt request (ir8), 2 endpoint 9 interrupt request (ir9) | 3 endpoint 10 interrupt request (ir10), 12 udc status/interrupt register 1 (usir1) -41, Usir1 bit definitions -41, Table 12-23 | Intel PXA255 User Manual | Page 441 / 598
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