Document Outline

• Intel® PXA255 Processor
  • Introduction 1
    • 1.1 Intel® XScale™ Microarchitecture Features
    • 1.2 System Integration Features
      • 1.2.1 Memory Controller
      • 1.2.2 Clocks and Power Controllers
      • 1.2.3 Universal Serial Bus (USB) Client
      • 1.2.4 DMA Controller (DMAC)
      • 1.2.5 LCD Controller
      • 1.2.6 AC97 Controller
      • 1.2.7 Inter-IC Sound (I2S) Controller
      • 1.2.8 Multimedia Card (MMC) Controller
      • 1.2.9 Fast Infrared (FIR) Communication Port
      • 1.2.10 Synchronous Serial Protocol Controller (SSPC)
      • 1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit
      • 1.2.12 GPIO
      • 1.2.13 UARTs
        • 1.2.13.1 Full Function UART (FFUART)
        • 1.2.13.2 Bluetooth UART (BTUART)
        • 1.2.13.3 Standard UART (STUART)
        • 1.2.13.4 Hardware UART (HWUART)
      • 1.2.14 Real-Time Clock (RTC)
      • 1.2.15 OS Timers
      • 1.2.16 Pulse-Width Modulator (PWM)
      • 1.2.17 Interrupt Control
      • 1.2.18 Network Synchronous Serial Protocol Port
  • System Architecture 2
    • 2.1 Overview
    • 2.2 Intel® XScale™ Microarchitecture Implementation Options
      • 2.2.1 Coprocessor 7 Register 4 - PSFS Bit
      • 2.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring
      • 2.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management
      • 2.2.4 Coprocessor 15 Register 0 - ID Register Definition
      • 2.2.5 Coprocessor 15 Register 1 - P-Bit
    • 2.3 I/O Ordering
    • 2.4 Semaphores
    • 2.5 Interrupts
    • 2.6 Reset
    • 2.7 Internal Registers
    • 2.8 Selecting Peripherals vs. General Purpose I/O
    • 2.9 Power on Reset and Boot Operation
    • 2.10 Power Management
    • 2.11 Pin List
    • 2.12 Memory Map
    • 2.13 System Architecture Register Summary
  • Clocks and Power Manager 3
    • 3.1 Clock Manager Introduction
    • 3.2 Power Manager Introduction
    • 3.3 Clock Manager
      • 3.3.1 32.768kHz Oscillator
      • 3.3.2 3.6864MHz Oscillator
      • 3.3.3 Core Phase Locked Loop
      • 3.3.4 95.85MHz Peripheral Phase Locked Loop
      • 3.3.5 147.46MHz Peripheral Phase Locked Loop
      • 3.3.6 Clock Gating
    • 3.4 Resets and Power Modes
      • 3.4.1 Hardware Reset
        • 3.4.1.1 Invoking Hardware Reset
        • 3.4.1.2 Behavior During Hardware Reset
        • 3.4.1.3 Completing Hardware Reset
      • 3.4.2 Watchdog Reset
        • 3.4.2.1 Invoking Watchdog Reset
        • 3.4.2.2 Behavior During Watchdog Reset
        • 3.4.2.3 Completing a Watchdog Reset
      • 3.4.3 GPIO Reset
        • 3.4.3.1 Invoking GPIO Reset
        • 3.4.3.2 Behavior During GPIO Reset
        • 3.4.3.3 Completing GPIO Reset
      • 3.4.4 Run Mode
      • 3.4.5 Turbo Mode
        • 3.4.5.1 Entering Turbo Mode
        • 3.4.5.2 Behavior in Turbo Mode
        • 3.4.5.3 Exiting Turbo Mode
      • 3.4.6 Idle Mode
        • 3.4.6.1 Entering Idle Mode
        • 3.4.6.2 Behavior in Idle Mode
        • 3.4.6.3 Exiting Idle Mode
      • 3.4.7 Frequency Change Sequence
        • 3.4.7.1 Preparing for a Frequency Change Sequence
        • 3.4.7.2 Invoking the Frequency Change Sequence
        • 3.4.7.3 Behavior During the Frequency Change Sequence
        • 3.4.7.4 Completing the Frequency Change Sequence
      • 3.4.8 33-MHz Idle Mode
        • 3.4.8.1 Entering 33-MHz Idle Mode
        • 3.4.8.2 Behavior in 33-MHz Idle Mode
        • 3.4.8.3 Exiting 33-MHz Idle Mode
      • 3.4.9 Sleep Mode
        • 3.4.9.1 Sleep Mode External Voltage Regulator Requirements
        • 3.4.9.2 Preparing for Sleep Mode
        • 3.4.9.3 Entering Sleep Mode
        • 3.4.9.4 Behavior in Sleep Mode
        • 3.4.9.5 Exiting Sleep Mode
      • 3.4.10 Power Mode Summary
    • 3.5 Power Manager Registers
      • 3.5.1 Power Manager Control Register (PMCR)
      • 3.5.2 Power Manager General Configuration Register (PCFR)
      • 3.5.3 Power Manager Wake-Up Enable Register (PWER)
      • 3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)
      • 3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)
      • 3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR)
      • 3.5.7 Power Manager Sleep Status Register (PSSR)
      • 3.5.8 Power Manager Scratch Pad Register (PSPR)
      • 3.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW)
      • 3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)
      • 3.5.11 Reset Controller Status Register (RCSR)
    • 3.6 Clocks Manager Registers
      • 3.6.1 Core Clock Configuration Register (CCCR)
      • 3.6.2 Clock Enable Register (CKEN)
      • 3.6.3 Oscillator Configuration Register (OSCC)
    • 3.7 Coprocessor 14: Clock and Power Management
      • 3.7.1 Core Clock Configuration Register (CCLKCFG)
      • 3.7.2 Power Mode Register (PWRMODE)
    • 3.8 External Hardware Considerations
      • 3.8.1 Power-On-Reset Considerations
      • 3.8.2 Power Supply Connectivity
      • 3.8.3 Driving the Crystal Pins from an External Clock Source
      • 3.8.4 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator
    • 3.9 Clocks and Power Manager Register Summary
      • 3.9.1 Clocks Manager Register Locations
      • 3.9.2 Power Manager Register Summary
  • System Integration Unit 4
    • 4.1 General-Purpose I/O
      • 4.1.1 GPIO Operation
      • 4.1.2 GPIO Alternate Functions
      • 4.1.3 GPIO Register Definitions
        • 4.1.3.1 GPIO Pin-Level Registers (GPLR0, GPLR1, GPLR2)
        • 4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)
        • 4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin Output Clear Registers (G...
        • 4.1.3.4 GPIO Rising Edge Detect Enable Registers (GRER0, GRER1, GRER2) and Falling Edge Detect En...
        • 4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)
        • 4.1.3.6 GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U, GAFR2_L, GAFR2_U)
        • 4.1.3.7 Example Procedure for Configuring the Alternate Function Registers
    • 4.2 Interrupt Controller
      • 4.2.1 Interrupt Controller Operation
      • 4.2.2 Interrupt Controller Register Definitions
        • 4.2.2.1 Interrupt Controller Mask Register (ICMR)
        • 4.2.2.2 Interrupt Controller Level Register (ICLR)
        • 4.2.2.3 Interrupt Controller Control Register (ICCR)
        • 4.2.2.4 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Register (ICFP)
        • 4.2.2.5 Interrupt Controller Pending Register (ICPR)
    • 4.3 Real-Time Clock (RTC)
      • 4.3.1 Real-Time Clock Operation
      • 4.3.2 RTC Register Definitions
        • 4.3.2.1 RTC Trim Register (RTTR)
        • 4.3.2.2 RTC Alarm Register (RTAR)
        • 4.3.2.3 RTC Counter Register (RCNR)
        • 4.3.2.4 RTC Status Register (RTSR)
      • 4.3.3 Trim Procedure
        • 4.3.3.1 Oscillator Frequency Calibration
        • 4.3.3.2 RTTR Value Calculations
    • 4.4 Operating System (OS) Timer
      • 4.4.1 Watchdog Timer Operation
      • 4.4.2 OS Timer Register Definitions
        • 4.4.2.1 OS Timer Match Register 0-3 (OSMRx)
        • 4.4.2.2 OS Timer Interrupt Enable Register (OIER)
        • 4.4.2.3 OS Timer Watchdog Match Enable Register (OWER)
        • 4.4.2.4 OS Timer Count Register (OSCR)
        • 4.4.2.5 OS Timer Status Register (OSSR)
    • 4.5 Pulse Width Modulator
      • 4.5.1 Pulse Width Modulator Operation
        • 4.5.1.1 Interdependencies
        • 4.5.1.2 Reset Sequence
        • 4.5.1.3 Power Management Requirements
      • 4.5.2 Register Descriptions
        • 4.5.2.1 PWM Control Registers (PWM_CTRLn)
        • 4.5.2.2 PWM Duty Cycle Registers (PWM_DUTYn)
        • 4.5.2.3 PWM Period Control Register (PWM_PERVALn)
      • 4.5.3 Pulse Width Modulator Output Wave Example
    • 4.6 System Integration Unit Register Summary
      • 4.6.1 GPIO Register Locations
      • 4.6.2 Interrupt Controller Register Locations
      • 4.6.3 Real-Time Clock Register Locations
      • 4.6.4 OS Timer Register Locations
      • 4.6.5 Pulse Width Modulator Register Locations
  • DMA Controller 5
    • 5.1 DMA Description
      • 5.1.1 DMAC Channels
      • 5.1.2 Signal Descriptions
        • 5.1.2.1 DREQ[1:0] and PREQ[37:0] Signals
        • 5.1.2.2 DMA_IRQ Signal
      • 5.1.3 DMA Channel Priority Scheme
      • 5.1.4 DMA Descriptors
        • 5.1.4.1 No-Descriptor Fetch Mode
        • 5.1.4.2 Descriptor Fetch Mode
        • 5.1.4.3 Servicing an Interrupt
      • 5.1.5 Channel States
      • 5.1.6 Read and Write Order
      • 5.1.7 Byte Transfer Order
      • 5.1.8 Trailing Bytes
    • 5.2 Transferring Data
      • 5.2.1 Servicing Internal Peripherals
        • 5.2.1.1 Using Flow-Through DMA Read Cycles to Service Internal Peripherals
        • 5.2.1.2 Using Flow-Through DMA Write Cycles to Service Internal Peripherals
      • 5.2.2 Quick Reference for DMA Programming
      • 5.2.3 Servicing Companion Chips and External Peripherals
        • 5.2.3.1 Using Flow-Through DMA Read Cycles to Service External Peripherals
        • 5.2.3.2 Using Flow-Through DMA Write Cycles to Service External Peripherals
      • 5.2.4 Memory-to-Memory Moves
    • 5.3 DMAC Registers
      • 5.3.1 DMA Interrupt Register (DINT)
      • 5.3.2 DMA Channel Control/Status Register (DCSRx)
      • 5.3.3 DMA Request to Channel Map Registers (DRCMRx)
      • 5.3.4 DMA Descriptor Address Registers (DDADRx)
      • 5.3.5 DMA Source Address Registers
      • 5.3.6 DMA Target Address Registers (DTADRx)
      • 5.3.7 DMA Command Registers (DCMDx)
    • 5.4 Examples
    • 5.5 DMA Controller Register Summary
  • Memory Controller 6
    • 6.1 Overview
    • 6.2 Functional Description
      • 6.2.1 SDRAM Interface Overview
      • 6.2.2 Static Memory Interface / Variable Latency I/O Interface
      • 6.2.3 16-Bit PC Card / Compact Flash Interface
    • 6.3 Memory System Examples
    • 6.4 Memory Accesses
      • 6.4.1 Reads and Writes
      • 6.4.2 Aborts and Nonexistent Memory
    • 6.5 Synchronous DRAM Memory Interface
      • 6.5.1 SDRAM MDCNFG Register (MDCNFG
      • 6.5.2 SDRAM Mode Register Set Configuration Register (MDMRS)
        • 6.5.2.1 Low-Power SDRAM Mode Register Set Configuration Register
      • 6.5.3 SDRAM MDREFR Register (MDREFR)
      • 6.5.4 Fixed-Delay or Return-Clock Data Latching
      • 6.5.5 SDRAM Memory Options
        • 6.5.5.1 SDRAM Addressing Modes
      • 6.5.6 SDRAM Command Overview
      • 6.5.7 SDRAM Waveforms
    • 6.6 Synchronous Static Memory Interface
      • 6.6.1 Synchronous Static Memory Configuration Register (SXCNFG)
        • 6.6.1.1 SMROM Memory Options
      • 6.6.2 Synchronous Static Memory Mode Register Set Configuration Register (SXMRS)
      • 6.6.3 Synchronous Static Memory Timing Diagrams
      • 6.6.4 Non-SDRAM Timing SXMEM Operation
        • 6.6.4.1 Non-SDRAM Timing Flash Read Timing Diagram
        • 6.6.4.2 K3 Synchronous StrataFlash Reset
    • 6.7 Asynchronous Static Memory
      • 6.7.1 Static Memory Interface
      • 6.7.2 Asynchronous Static Memory Control Registers (MSCx)
      • 6.7.3 ROM Interface
        • 6.7.3.1 ROM Timing Diagrams and Parameters
      • 6.7.4 SRAM Interface Overview
        • 6.7.4.1 SRAM Timing Diagrams and Parameters
      • 6.7.5 Variable Latency I/O (VLIO) Interface Overview
        • 6.7.5.1 Variable Latency I/O Timing Diagrams and Parameters
      • 6.7.6 FLASH Memory Interface
        • 6.7.6.1 FLASH Memory Timing Diagrams and Parameters
    • 6.8 16-Bit PC Card/Compact Flash Interface
      • 6.8.1 Expansion Memory Timing Configuration Register
      • 6.8.2 Expansion Memory Configuration Register (MECR)
      • 6.8.3 16-Bit PC Card Overview
      • 6.8.4 External Logic for 16-Bit PC Card Implementation
      • 6.8.5 Expansion Card Interface Timing Diagrams and Parameters
    • 6.9 Companion Chip Interface
      • 6.9.1 Alternate Bus Master Mode
        • 6.9.1.1 GPIO Reset
        • 6.9.1.2 nVDD_FAULT/nBATT_FAULT with PMCR[IDAE] Disabled
        • 6.9.1.3 nVDD_FAULT/nBATT_FAULT with PMCR[IDAE] Enabled
    • 6.10 Options and Settings for Boot Memory
      • 6.10.1 Alternate Booting
      • 6.10.2 Boot Time Defaults
        • 6.10.2.1 BOOT_DEF Read-Only Register (BOOT_DEF)
        • 6.10.2.2 Boot-Time Configurations
      • 6.10.3 Memory Interface Reset and Initialization
    • 6.11 Hardware, Watchdog, or Sleep Reset Operation
    • 6.12 GPIO Reset Procedure
    • 6.13 Memory Controller Register Summary
  • LCD Controller 7
    • 7.1 Overview
      • 7.1.1 Features
      • 7.1.2 Pin Descriptions
    • 7.2 LCD Controller Operation
      • 7.2.1 Enabling the Controller
      • 7.2.2 Disabling the Controller
      • 7.2.3 Resetting the Controller
    • 7.3 Detailed Module Descriptions
      • 7.3.1 Input FIFOs
      • 7.3.2 Lookup Palette
      • 7.3.3 Temporal Modulated Energy Distribution (TMED) Dithering
      • 7.3.4 Output FIFOs
      • 7.3.5 LCD Controller Pin Usage
        • 7.3.5.1 Passive Display Timing
        • 7.3.5.2 Active Display Timing
        • 7.3.5.3 Pixel Data Pins (L_DDx)
      • 7.3.6 DMA
    • 7.4 LCD External Palette and Frame Buffers
      • 7.4.1 External Palette Buffer
      • 7.4.2 External Frame Buffer
    • 7.5 Functional Timing
    • 7.6 Register Descriptions
      • 7.6.1 LCD Controller Control Register 0 (LCCR0)
      • 7.6.2 LCD Controller Control Register 1 (LCCR1)
      • 7.6.3 LCD Controller Control Register 2 (LCCR2)
      • 7.6.4 LCD Controller Control Register 3 (LCCR3)
      • 7.6.5 LCD Controller DMA
        • 7.6.5.1 Frame Descriptors
        • 7.6.5.2 LCD DMA Frame Descriptor Address Registers (FDADRx)
        • 7.6.5.3 LCD DMA Frame Source Address Registers (FSADRx)
        • 7.6.5.4 LCD DMA Frame ID Registers (FIDRx)
        • 7.6.5.5 LCD DMA Command Registers (LDCMDx)
      • 7.6.6 LCD DMA Frame Branch Registers (FBRx)
      • 7.6.7 LCD Controller Status Register (LCSR)
      • 7.6.8 LCD Controller Interrupt ID Register (LIIDR)
      • 7.6.9 TMED RGB Seed Register (TRGBR)
      • 7.6.10 TMED Control Register (TCR)
    • 7.7 LCD Controller Register Summary
  • Synchronous Serial Port Controller 8
    • 8.1 Overview
    • 8.2 Signal Description
      • 8.2.1 External Interface to Synchronous Serial Peripherals
    • 8.3 Functional Description
      • 8.3.1 Data Transfer
    • 8.4 Data Formats
      • 8.4.1 Serial Data Formats for Transfer to/from Peripherals
        • 8.4.1.1 SSP Format Details
        • 8.4.1.2 SPI Format Details
        • 8.4.1.3 Microwire Format Details
      • 8.4.2 Parallel Data Formats for FIFO Storage
    • 8.5 FIFO Operation and Data Transfers
      • 8.5.1 Using Programmed I/O Data Transfers
      • 8.5.2 Using DMA Data Transfers
    • 8.6 Baud-Rate Generation
    • 8.7 SSP Serial Port Registers
      • 8.7.1 SSP Control Register 0 (SSCR0)
        • 8.7.1.1 Data Size Select (DSS)
        • 8.7.1.2 Frame Format (FRF)
        • 8.7.1.3 External Clock Select (ECS)
        • 8.7.1.4 Synchronous Serial Port Enable (SSE)
        • 8.7.1.5 Serial Clock Rate (SCR)
      • 8.7.2 SSP Control Register 1 (SSCR1)
        • 8.7.2.1 Receive FIFO Interrupt Enable (RIE)
        • 8.7.2.2 Transmit FIFO Interrupt Enable (TIE)
        • 8.7.2.3 Loop Back Mode (LBM)
        • 8.7.2.4 Serial Clock Polarity (SPO)
        • 8.7.2.5 Serial Clock Phase (SPH)
        • 8.7.2.6 Microwire Transmit Data Size (MWDS)
        • 8.7.2.7 Transmit FIFO Interrupt/DMA Threshold (TFT)
        • 8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT)
      • 8.7.3 SSP Data Register (SSDR)
      • 8.7.4 SSP Status Register (SSSR)
        • 8.7.4.1 Transmit FIFO Not Full Flag (TNF)
        • 8.7.4.2 Receive FIFO Not Empty Flag (RNE)
        • 8.7.4.3 SSP Busy Flag (BSY)
        • 8.7.4.4 Transmit FIFO Service Request Flag (TFS)
        • 8.7.4.5 Receive FIFO Service Request Flag (RFS)
        • 8.7.4.6 Receiver Overrun Status (ROR)
        • 8.7.4.7 Transmit FIFO Level (TFL)
        • 8.7.4.8 Receive FIFO Level (RFL)
    • 8.8 SSP Controller Register Summary
  • I2C Bus Interface Unit 9
    • 9.1 Overview
    • 9.2 Signal Description
    • 9.3 Functional Description
      • 9.3.1 Operational Blocks
      • 9.3.2 I2C Bus Interface Modes
      • 9.3.3 Start and Stop Bus States
        • 9.3.3.1 START Condition
        • 9.3.3.2 No START or STOP Condition
        • 9.3.3.3 STOP Condition
    • 9.4 I2C Bus Operation
      • 9.4.1 Serial Clock Line (SCL) Generation
      • 9.4.2 Data and Addressing Management
        • 9.4.2.1 Addressing a Slave Device
      • 9.4.3 I2C Acknowledge
      • 9.4.4 Arbitration
        • 9.4.4.1 SCL Arbitration
        • 9.4.4.2 SDA Arbitration
      • 9.4.5 Master Operations
      • 9.4.6 Slave Operations
      • 9.4.7 General Call Address
    • 9.5 Slave Mode Programming Examples
      • 9.5.1 Initialize Unit
      • 9.5.2 Write n Bytes as a Slave
      • 9.5.3 Read n Bytes as a Slave
    • 9.6 Master Programming Examples
      • 9.6.1 Initialize Unit
      • 9.6.2 Write 1 Byte as a Master
      • 9.6.3 Read 1 Byte as a Master
      • 9.6.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master
      • 9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort
    • 9.7 Glitch Suppression Logic
    • 9.8 Reset Conditions
    • 9.9 Register Definitions
      • 9.9.1 I2C Bus Monitor Register (IBMR)
      • 9.9.2 I2C Data Buffer Register (IDBR)
      • 9.9.3 I2C Control Register (ICR)
      • 9.9.4 I2C Status Register (ISR)
      • 9.9.5 I2C Slave Address Register (ISAR)
  • UARTs 10
    • 10.1 Feature List
    • 10.2 Overview
      • 10.2.1 Full Function UART
      • 10.2.2 Bluetooth UART
      • 10.2.3 Standard UART
      • 10.2.4 Compatibility with 16550
    • 10.3 Signal Descriptions
    • 10.4 UART Operational Description
      • 10.4.1 Reset
      • 10.4.2 Internal Register Descriptions
        • 10.4.2.1 Receive Buffer Register (RBR)
        • 10.4.2.2 Transmit Holding Register (THR)
        • 10.4.2.3 Divisor Latch Registers (DLL and DLH)
        • 10.4.2.4 Interrupt Enable Register (IER)
        • 10.4.2.5 Interrupt Identification Register (IIR)
        • 10.4.2.6 FIFO Control Register (FCR)
        • 10.4.2.7 Line Control Register (LCR)
        • 10.4.2.8 Line Status Register (LSR)
        • 10.4.2.9 Modem Control Register (MCR)
        • 10.4.2.10 Modem Status Register (MSR)
        • 10.4.2.11 Scratchpad Register (SPR)
      • 10.4.3 FIFO Interrupt Mode Operation
        • 10.4.3.1 Receive Interrupt
        • 10.4.3.2 Character Timeout Indication Interrupt
        • 10.4.3.3 Transmit Interrupt
      • 10.4.4 FIFO Polled Mode Operation
      • 10.4.5 DMA Requests
        • 10.4.5.1 Trailing Bytes in the Receive FIFO
      • 10.4.6 Slow Infrared Asynchronous Interface
        • 10.4.6.1 Infrared Selection Register (ISR)
        • 10.4.6.2 Operation
    • 10.5 UART Register Summary
      • 10.5.1 UART Register Differences
  • Fast Infrared Communication Port 11
    • 11.1 Signal Description
    • 11.2 FICP Operation
      • 11.2.1 4PPM Modulation
      • 11.2.2 Frame Format
      • 11.2.3 Address Field
      • 11.2.4 Control Field
      • 11.2.5 Data Field
      • 11.2.6 CRC Field
      • 11.2.7 Baud Rate Generation
      • 11.2.8 Receive Operation
      • 11.2.9 Transmit Operation
      • 11.2.10 Transmit and Receive FIFOs
      • 11.2.11 Trailing or Error Bytes in the Receive FIFO
    • 11.3 FICP Register Definitions
      • 11.3.1 FICP Control Register 0 (ICCR0)
      • 11.3.2 FICP Control Register 1 (ICCR1)
      • 11.3.3 FICP Control Register 2 (ICCR2)
      • 11.3.4 FICP Data Register (ICDR)
      • 11.3.5 FICP Status Register 0 (ICSR0)
      • 11.3.6 FICP Status Register 1 (ICSR1)
    • 11.4 FICP Register Summary
  • USB Device Controller 12
    • 12.1 USB Overview
    • 12.2 Device Configuration
    • 12.3 USB Protocol
      • 12.3.1 Signalling Levels
      • 12.3.2 Bit Encoding
      • 12.3.3 Field Formats
      • 12.3.4 Packet Formats
        • 12.3.4.1 Token Packet Type
        • 12.3.4.2 Start of Frame Packet Type
        • 12.3.4.3 Data Packet Type
        • 12.3.4.4 Handshake Packet Type
      • 12.3.5 Transaction Formats
        • 12.3.5.1 Bulk Transaction Type
        • 12.3.5.2 Isochronous Transaction Type
        • 12.3.5.3 Control Transaction Type
        • 12.3.5.4 Interrupt Transaction Type
      • 12.3.6 UDC Device Requests
      • 12.3.7 Configuration
    • 12.4 UDC Hardware Connection
      • 12.4.1 Self-Powered Device
        • 12.4.1.1 When GPIOn and GPIOx are Different Pins
        • 12.4.1.2 When GPIOn and GPIOx are the Same Pin
      • 12.4.2 Bus-Powered Devices
    • 12.5 UDC Operation
      • 12.5.1 Case 1: EP0 Control Read
      • 12.5.2 Case 2: EP0 Control Read with a Premature Status Stage
      • 12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage
      • 12.5.4 Case 4: EP0 No Data Command
      • 12.5.5 Case 5: EP1 Data Transmit (BULK-IN)
        • 12.5.5.1 Software Enables the DMA
        • 12.5.5.2 Software Enables the EP1 Interrupt
      • 12.5.6 Case 6: EP2 Data Receive (BULK-OUT)
        • 12.5.6.1 Software Enables the DMA
        • 12.5.6.2 Software Allows the Megacell to Handle the Transaction
      • 12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)
        • 12.5.7.1 Software Enables DMA
        • 12.5.7.2 Software Enables the EP3 Interrupt
        • 12.5.7.3 Software Enables the SOF Interrupt
      • 12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)
        • 12.5.8.1 Software Enables the DMA
        • 12.5.8.2 Software Allows the Megacell to Handle the Transaction
        • 12.5.8.3 Software Enables the SOF Interrupt
      • 12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN)
      • 12.5.10 Case 10: RESET Interrupt
      • 12.5.11 Case 11: SUSPEND Interrupt
      • 12.5.12 Case 12: RESUME Interrupt
    • 12.6 UDC Register Definitions
      • 12.6.1 UDC Control Register (UDCCR)
        • 12.6.1.1 UDC Enable (UDE)
        • 12.6.1.2 UDC Active (UDA)
        • 12.6.1.3 UDC Resume (RSM)
        • 12.6.1.4 Resume Interrupt Request (RESIR)
        • 12.6.1.5 Suspend Interrupt Request (SUSIR)
        • 12.6.1.6 Suspend/Resume Interrupt Mask (SRM)
        • 12.6.1.7 Reset Interrupt Request (RSTIR)
        • 12.6.1.8 Reset Interrupt Mask (REM)
      • 12.6.2 UDC Control Function Register (UDCCFR)
        • 12.6.2.1 ACK Control Mode
        • 12.6.2.2 ACK Response Enable
      • 12.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0)
        • 12.6.3.1 OUT Packet Ready (OPR)
        • 12.6.3.2 IN Packet Ready (IPR)
        • 12.6.3.3 Flush Tx FIFO (FTF)
        • 12.6.3.4 Device Remote Wakeup Feature (DRWF)
        • 12.6.3.5 Sent Stall (SST)
        • 12.6.3.6 Force Stall (FST)
        • 12.6.3.7 Receive FIFO Not Empty (RNE)
        • 12.6.3.8 Setup Active (SA)
      • 12.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11)
        • 12.6.4.1 Transmit FIFO Service (TFS)
        • 12.6.4.2 Transmit Packet Complete (TPC)
        • 12.6.4.3 Flush Tx FIFO (FTF)
        • 12.6.4.4 Transmit Underrun (TUR)
        • 12.6.4.5 Sent STALL (SST)
        • 12.6.4.6 Force STALL (FST)
        • 12.6.4.7 Bit 6 Reserved
        • 12.6.4.8 Transmit Short Packet (TSP)
      • 12.6.5 UDC Endpoint x Control/Status Register (UDCCS2/7/12)
        • 12.6.5.1 Receive FIFO Service (RFS)
        • 12.6.5.2 Receive Packet Complete (RPC)
        • 12.6.5.3 Bit 2 Reserved
        • 12.6.5.4 DMA Enable (DME)
        • 12.6.5.5 Sent Stall (SST)
        • 12.6.5.6 Force Stall (FST)
        • 12.6.5.7 Receive FIFO Not Empty (RNE)
        • 12.6.5.8 Receive Short Packet (RSP)
      • 12.6.6 UDC Endpoint x Control/Status Register (UDCCS3/8/13)
        • 12.6.6.1 Transmit FIFO Service (TFS)
        • 12.6.6.2 Transmit Packet Complete (TPC)
        • 12.6.6.3 Flush Tx FIFO (FTF)
        • 12.6.6.4 Transmit Underrun (TUR)
        • 12.6.6.5 Bits 6:4 Reserved
        • 12.6.6.6 Transmit Short Packet (TSP)
      • 12.6.7 UDC Endpoint x Control/Status Register (UDCCS4/9/14)
        • 12.6.7.1 Receive FIFO Service (RFS)
        • 12.6.7.2 Receive Packet Complete (RPC)
        • 12.6.7.3 Receive Overflow (ROF)
        • 12.6.7.4 DMA Enable (DME)
        • 12.6.7.5 Bits 5:4 Reserved
        • 12.6.7.6 Receive FIFO Not Empty (RNE)
        • 12.6.7.7 Receive Short Packet (RSP)
      • 12.6.8 UDC Endpoint x Control/Status Register (UDCCS5/10/15)
        • 12.6.8.1 Transmit FIFO Service (TFS)
        • 12.6.8.2 Transmit Packet Complete (TPC)
        • 12.6.8.3 Flush Tx FIFO (FTF)
        • 12.6.8.4 Transmit Underrun (TUR)
        • 12.6.8.5 Sent STALL (SST)
        • 12.6.8.6 Force STALL (FST)
        • 12.6.8.7 Bit 6 Reserved
        • 12.6.8.8 Transmit Short Packet (TSP)
      • 12.6.9 UDC Interrupt Control Register 0 (UICR0)
        • 12.6.9.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7
      • 12.6.10 UDC Interrupt Control Register 1 (UICR1)
        • 12.6.10.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15.
      • 12.6.11 UDC Status/Interrupt Register 0 (USIR0)
        • 12.6.11.1 Endpoint 0 Interrupt Request (IR0)
        • 12.6.11.2 Endpoint 1 Interrupt Request (IR1)
        • 12.6.11.3 Endpoint 2 Interrupt Request (IR2)
        • 12.6.11.4 Endpoint 3 Interrupt Request (IR3)
        • 12.6.11.5 Endpoint 4 Interrupt Request (IR4)
        • 12.6.11.6 Endpoint 5 Interrupt Request (IR5)
        • 12.6.11.7 Endpoint 6 Interrupt Request (IR6)
        • 12.6.11.8 Endpoint 7 Interrupt Request (IR7)
      • 12.6.12 UDC Status/Interrupt Register 1 (USIR1)
        • 12.6.12.1 Endpoint 8 Interrupt Request (IR8)
        • 12.6.12.2 Endpoint 9 Interrupt Request (IR9)
        • 12.6.12.3 Endpoint 10 Interrupt Request (IR10)
        • 12.6.12.4 Endpoint 11 Interrupt Request (IR11)
        • 12.6.12.5 Endpoint 12 Interrupt Request (IR12)
        • 12.6.12.6 Endpoint 13 Interrupt Request (IR13)
        • 12.6.12.7 Endpoint 14 Interrupt Request (IR14)
        • 12.6.12.8 Endpoint 15 Interrupt Request (IR15)
      • 12.6.13 UDC Frame Number High Register (UFNHR)
        • 12.6.13.1 UDC Frame Number MSB (FNMSB)
        • 12.6.13.2 Isochronous Packet Error Endpoint 4 (IPE4)
        • 12.6.13.3 Isochronous Packet Error Endpoint 9 (IPE9)
        • 12.6.13.4 Isochronous Packet Error Endpoint 14 (IPE14)
        • 12.6.13.5 Start of Frame Interrupt Mask (SIM)
        • 12.6.13.6 Start of Frame Interrupt Request (SIR)
      • 12.6.14 UDC Frame Number Low Register (UFNLR)
      • 12.6.15 UDC Byte Count Register x (UBCR2/4/7/9/12/14)
        • 12.6.15.1 Endpoint x Byte Count (BC)
      • 12.6.16 UDC Endpoint 0 Data Register (UDDR0)
      • 12.6.17 UDC Endpoint x Data Register (UDDR1/6/11)
      • 12.6.18 UDC Endpoint x Data Register (UDDR2/7/12)
      • 12.6.19 UDC Endpoint x Data Register (UDDR3/8/13)
      • 12.6.20 UDC Endpoint x Data Register (UDDR4/9/14)
      • 12.6.21 UDC Endpoint x Data Register (UDDR5/10/15)
    • 12.7 USB Device Controller Register Summary
  • AC’97 Controller Unit 13
    • 13.1 Overview
    • 13.2 Feature List
    • 13.3 Signal Description
      • 13.3.1 Signal Configuration Steps
      • 13.3.2 Example AC-link
    • 13.4 AC-link Digital Serial Interface Protocol
      • 13.4.1 AC-link Audio Output Frame (SDATA_OUT)
        • 13.4.1.1 Slot 0: Tag Phase
        • 13.4.1.2 Slot 1: Command Address Port
        • 13.4.1.3 Slot 2: Command Data Port
        • 13.4.1.4 Slot 3: PCM Playback Left Channel
        • 13.4.1.5 Slot 4: PCM Playback Right Channel
        • 13.4.1.6 Slot 5: Modem Line CODEC
        • 13.4.1.7 Slots 6-11: Reserved
        • 13.4.1.8 Slot 12: I/O Control
      • 13.4.2 AC-link Audio Input Frame (SDATA_IN)
        • 13.4.2.1 Slot 0: Tag Phase
        • 13.4.2.2 Slot 1: Status Address Port/SLOTREQ bits
        • 13.4.2.3 Slot 2: Status Data Port
        • 13.4.2.4 Slot 3: PCM Record Left Channel
        • 13.4.2.5 Slot 4: PCM Record Right Channel
        • 13.4.2.6 Slot 5: Optional Modem Line CODEC
        • 13.4.2.7 Slot 6: Optional Dedicated Microphone Record Data
        • 13.4.2.8 Slots 7-11: Reserved
        • 13.4.2.9 Slot 12: I/O Status
    • 13.5 AC-link Low Power Mode
      • 13.5.1 Powering Down the AC-link
      • 13.5.2 Waking up the AC-link
        • 13.5.2.1 Wake up triggered by the CODEC
        • 13.5.2.2 Wake Up Triggered by the ACUNIT
    • 13.6 ACUNIT Operation
      • 13.6.1 Initialization
      • 13.6.2 Trailing bytes
      • 13.6.3 Operational Flow for Accessing CODEC Registers
    • 13.7 Clocks and Sampling Frequencies
    • 13.8 Functional Description
      • 13.8.1 FIFOs
        • 13.8.1.1 Transmit FIFO Errors
        • 13.8.1.2 Receive FIFO Errors
      • 13.8.2 Interrupts
      • 13.8.3 Registers
        • 13.8.3.1 Global Control Register (GCR)
        • 13.8.3.2 Global Status Register (GSR)
        • 13.8.3.3 PCM-Out Control Register (POCR)
        • 13.8.3.4 PCM-In Control Register (PICR)
        • 13.8.3.5 PCM-Out Status Register (POSR)
        • 13.8.3.6 PCM_In Status Register (PISR)
        • 13.8.3.7 CODEC Access Register (CAR) This is a read/write register. Ignore reads from reserved bi...
        • 13.8.3.8 PCM Data Register (PCDR) This is a read/write register. Ignore reads from reserved bits....
        • 13.8.3.9 Mic-In Control Register (MCCR)
        • 13.8.3.10 Mic-In Status Register (MCSR)
        • 13.8.3.11 Mic-In Data Register (MCDR)
        • 13.8.3.12 Modem-Out Control Register (MOCR)
        • 13.8.3.13 Modem-In Control Register (MICR)
        • 13.8.3.14 Modem-Out Status Register (MOSR)
        • 13.8.3.15 Modem-In Status Register (MISR)
        • 13.8.3.16 Modem Data Register (MODR)
        • 13.8.3.17 Accessing CODEC Registers
    • 13.9 AC’97 Register Summary
  • Inter-Integrated-Circuit Sound (I2S) Controller 14
    • 14.1 Overview
    • 14.2 Signal Descriptions
    • 14.3 Controller Operation
      • 14.3.1 Initialization
      • 14.3.2 Disabling and Enabling Audio Replay
      • 14.3.3 Disabling and Enabling Audio Record
      • 14.3.4 Transmit FIFO Errors
      • 14.3.5 Receive FIFO Errors
      • 14.3.6 Trailing Bytes
    • 14.4 Serial Audio Clocks and Sampling Frequencies
    • 14.5 Data Formats
      • 14.5.1 FIFO and Memory Format
      • 14.5.2 I2S and MSB-Justified Serial Audio Formats
    • 14.6 Registers
      • 14.6.1 Serial Audio Controller Global Control Register (SACR0)
        • 14.6.1.1 Special purpose FIFO Read/Write function
        • 14.6.1.2 Suggested TFTH and RFTH for DMA servicing
      • 14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1)
      • 14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)
      • 14.6.4 Serial Audio Clock Divider Register (SADIV)
      • 14.6.5 Serial Audio Interrupt Clear Register (SAICR)
      • 14.6.6 Serial Audio Interrupt Mask Register (SAIMR)
      • 14.6.7 Serial Audio Data Register (SADR)
    • 14.7 Interrupts
    • 14.8 I2S Controller Register Summary
  • MultiMediaCard Controller 15
    • 15.1 Overview
    • 15.2 MMC Controller Functional Description
      • 15.2.1 Signal Description
      • 15.2.2 MMC Controller Reset
      • 15.2.3 Card Initialization Sequence
      • 15.2.4 MMC and SPI Modes
        • 15.2.4.1 MMC Mode
        • 15.2.4.2 SPI Mode
      • 15.2.5 Error Detection
      • 15.2.6 Interrupts
      • 15.2.7 Clock Control
      • 15.2.8 Data FIFOs
        • 15.2.8.1 Response Data FIFO (MMC_RES)
        • 15.2.8.2 Receive Data FIFO, MMC_RXFIFO
        • 15.2.8.3 Transmit Data FIFO, MMC_TXFIFO
        • 15.2.8.4 DMA and Program I/O
    • 15.3 Card Communication Protocol
      • 15.3.1 Basic, No Data, Command and Response Sequence
      • 15.3.2 Data Transfer
        • 15.3.2.1 Block Data Write
        • 15.3.2.2 Block Data Read
        • 15.3.2.3 Stream Data Write
        • 15.3.2.4 Stream Data READ
      • 15.3.3 Busy Sequence
      • 15.3.4 SPI Functionality
    • 15.4 MultiMediaCard Controller Operation
      • 15.4.1 Start and Stop Clock
      • 15.4.2 Initialize
      • 15.4.3 Enabling SPI Mode
      • 15.4.4 No Data Command and Response Sequence
      • 15.4.5 Erase
      • 15.4.6 Single Data Block Write
      • 15.4.7 Single Block Read
      • 15.4.8 Multiple Block Write
      • 15.4.9 Multiple Block Read
      • 15.4.10 Stream Write
      • 15.4.11 Stream Read
    • 15.5 MMC Controller Registers
      • 15.5.1 MMC_STRPCL Register
      • 15.5.2 MMC_Status Register (MMC_STAT)
      • 15.5.3 MMC_CLKRT Register (MMC_CLKRT)
      • 15.5.4 MMC_SPI Register (MMC_SPI)
      • 15.5.5 MMC_CMDAT Register (MMC_CMDAT)
      • 15.5.6 MMC_RESTO Register (MMC_RESTO)
      • 15.5.7 MMC_RDTO Register (MMC_RDTO)
      • 15.5.8 MMC_BLKLEN Register (MMC_BLKLEN)
      • 15.5.9 MMC_NOB Register (MMC_NOB)
      • 15.5.10 MMC_PRTBUF Register (MMC_PRTBUF)
      • 15.5.11 MMC_I_MASK Register (MMC_I_MASK)
      • 15.5.12 MMC_I_REG Register (MMC_I_REG)
      • 15.5.13 MMC_CMD Register (MMC_CMD)
      • 15.5.14 MMC_ARGH Register (MMC_ARGH)
      • 15.5.15 MMC_ARGL Register (MMC_ARGL)
      • 15.5.16 MMC_RES FIFO
      • 15.5.17 MMC_RXFIFO FIFO
      • 15.5.18 MMC_TXFIFO FIFO
    • 15.6 MultiMediaCard Controller Register Summary
  • Network SSP Serial Port 16
    • 16.1 Overview
    • 16.2 Features
    • 16.3 Signal Description
    • 16.4 Operation
      • 16.4.1 Processor and DMA FIFO Access
      • 16.4.2 Trailing Bytes in the Receive FIFO
        • 16.4.2.1 Time-out
        • 16.4.2.2 Removing Trailing Bytes
      • 16.4.3 Data Formats
        • 16.4.3.1 TI Synchronous Serial Protocol* Details
        • 16.4.3.2 SPI Protocol Details
        • 16.4.3.3 Microwire* Protocol Details
        • 16.4.3.4 PSP Details
      • 16.4.4 Hi-Z on SSPTXD
        • 16.4.4.1 TI Synchronous Serial Port
        • 16.4.4.2 Motorola SPI
        • 16.4.4.3 National Semiconductor Microwire
        • 16.4.4.4 Programmable Serial Protocol
      • 16.4.5 FIFO Operation
        • 16.4.5.1 Using Programmed I/O Data Transfers
        • 16.4.5.2 Using DMA Data Transfers
      • 16.4.6 Baud-Rate Generation
    • 16.5 Register Descriptions
      • 16.5.1 SSP Control Register 0 (SSCR0)
      • 16.5.2 SSP Control Register 1 (SSCR1)
      • 16.5.3 SSP Programmable Serial Protocol Register (SSPSP)
      • 16.5.4 SSP Time Out Register (SSTO)
      • 16.5.5 SSP Interrupt Test Register (SSITR)
      • 16.5.6 SSP Status Register (SSSR)
      • 16.5.7 SSP Data Register (SSDR)
    • 16.6 Network SSP Serial Port Register Summary
  • Hardware UART 17
    • 17.1 Overview
    • 17.2 Features
    • 17.3 Signal Descriptions
    • 17.4 Operation
      • 17.4.1 Reset
      • 17.4.2 FIFO Operation
        • 17.4.2.1 FIFO Interrupt Mode Operation
        • 17.4.2.2 FIFO Polled Mode Operation
        • 17.4.2.3 FIFO DMA Mode Operation
        • 17.4.2.4 DMA Receive Programming Errors
        • 17.4.2.5 DMA Error Handling
        • 17.4.2.6 Removing Trailing Bytes In DMA Mode
      • 17.4.3 Autoflow Control
      • 17.4.4 Auto-Baud-Rate Detection
      • 17.4.5 Slow Infrared Asynchronous Interface
        • 17.4.5.1 Operation
    • 17.5 Register Descriptions
      • 17.5.1 Receive Buffer Register (RBR)
      • 17.5.2 Transmit Holding Register (THR)
      • 17.5.3 Divisor Latch Registers (DLL and DLH)
      • 17.5.4 Interrupt Enable Register (IER)
      • 17.5.5 Interrupt Identification Register (IIR)
      • 17.5.6 FIFO Control Register (FCR)
      • 17.5.7 Receive FIFO Occupancy Register (FOR)
      • 17.5.8 Auto-Baud Control Register (ABR)
      • 17.5.9 Auto-Baud Count Register (ACR)
      • 17.5.10 Line Control Register (LCR)
      • 17.5.11 Line Status Register (LSR)
      • 17.5.12 Modem Control Register (MCR)
      • 17.5.13 Modem Status Register (MSR)
      • 17.5.14 Scratchpad Register (SCR)
      • 17.5.15 Infrared Selection Register (ISR)
    • 17.6 Hardware UART Register Summary