Bit sdr mode with a source synchronous txclk, Figure 14–1, Refclk is used as the clk125_in for the core – Altera IP Compiler for PCI Express User Manual

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Bit sdr mode with a source synchronous txclk, Figure 14–1, Refclk is used as the clk125_in for the core | Altera IP Compiler for PCI Express User Manual | Page 222 / 372 Bit sdr mode with a source synchronous txclk, Figure 14–1, Refclk is used as the clk125_in for the core | Altera IP Compiler for PCI Express User Manual | Page 222 / 372
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