Altera IP Compiler for PCI Express - Manual (Page 218)

13–8 Chapter 13: Reconfiguration and Offset Cancellation
Dynamic Reconfiguration
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
0xAA 15:0 BAR4[159:144]. b’0
0xAB
BAR5[191:160]. b’0
0 BAR5[160]: I/O Space. b’0
2:1
BAR5[162:161]: Memory Space (see bit settings for
BAR0).
b’0
3 BAR5[163]: Prefetchable. b’0
BAR5[191:164]: Bar size mask. b’0
15:4 BAR5[175:164]. b’0
0xAC 15:0 BAR5[191:176]. b’0
0xAD 15:0
Expansion BAR[223:192]: Bar size mask. b’0
Expansion BAR[207:192]. b’0
0xAE 15:0 Expansion BAR[223:208]. b’0
0xAF
1:0
IO.
b’0
Table 6–3 on page 6–3
00: no IO windows.
01: IO 16 bit.
11: IO 32-bit.
3:2
Prefetchable.
b’0
00: not implemented.
01: prefetchable 32.
11: prefetchable 64.
15:4 Reserved. —
B0
5:0 Reserved — —
6
Selectable de-emphasis, operates as specified in the PCI
Express Base Specification when operating at the 5.0GT/s
rate:
1: 3.5 dB
0: -6 dB.
This setting has no effect when operating at the 2.5GT/s
rate.
9:7
Transmit Margin. Directly drives the transceiver
tx_pipemargin
bits. Refer to the transceiver
documentation for the appropriate device handbook to
determine what V
OD
settings are available as follows:
Arria II Device Data Sheet and Addendum in volume 3 of
the Arria II Device Handbook, Cyclone IV Device
Datasheet in volume 3 of the Cyclone IV Device
Handbook, or Stratix IV Dynamic Reconfiguration in
volume 3 of the Stratix IV Handbook.
0xB1-FF Reserved.
Table 13–1. Dynamically Reconfigurable Registers in the Hard IP Implementation (Part 7 of 7)
Address Bits Description Default
Value
Additional Information