Altera IP Compiler for PCI Express - Manual (Page 258)

15–26 Chapter 15: Testbench and Design Example
Root Port BFM
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Root Port BFM
The basic root port BFM provides a VHDL procedure-based or Verilog HDL
task-based interface for requesting transactions that are issued to the PCI Express link.
The root port BFM also handles requests received from the PCI Express link.
Figure 15–6 provides an overview of the root port BFM.
The functionality of each of the modules included in Figure 15–6 is explained below.
■ BFM shared memory (altpcietb_bfm_shmem VHDL package or Verilog HDL
include file)—The root port BFM is based on the BFM memory that is used for the
following purposes:
■ Storing data received with all completions from the PCI Express link.
■ Storing data received with all write transactions received from the PCI Express
link.
■ Sourcing data for all completions in response to read transactions received
from the PCI Express link.
■ Sourcing data for most write transactions issued to the PCI Express link. The
only exception is certain BFM write procedures that have a four-byte field of
write data passed in the call.
■ Storing a data structure that contains the sizes of and the values programmed
in the BARs of the endpoint.
A set of procedures is provided to read, write, fill, and check the shared memory from
the BFM driver. For details on these procedures, see
“BFM Shared Memory Access
Procedures” on page 15–40 .
■ BFM Read/Write Request Procedures/Functions (altpcietb_bfm_rdwr VHDL
package or Verilog HDL include file)— This package provides the basic BFM
procedure calls for PCI Express read and write requests. For details on these
procedures, see
“BFM Read and Write Procedures” on page 15–34 .
Figure 15–6. Root Port BFM
BFM Shared Memory
(altpcietb_bfm_shmem)
BFM Read/Write Shared
Request Procedures
(altpcietb_bfm_rdwr)
BFM Configuration
Procedures
(altpcietb_bfm_configure)
BFM Log Interface
(altpcietb_bfm_log)
BFM Request Interface
(altpcietb_bfm_req_intf)
Root Port RTL Model (altpcietb_bfm_rp_top_x8_pipen1b)
IP Functional Simulation
Model of the Root
Port Interface
(altpcietb_bfm_rpvar_64b_x8_pipen1b)
VC0 Interface
(altpcietb_bfm_vcintf)
VC1 Interface
(altpcietb_bfm_vcintf)
Root Port BFM