Altera IP Compiler for PCI Express - Manual (Page 43)

Chapter 3: Parameter Settings 3–7
Parameters in the Qsys Design Flow
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Address Translation
The Address Translation section of the Qsys design flow IP Compiler for PCI Express
parameter editor contains parameter settings for address translation in the PCI
Express Avalon-MM bridge.
Table 3–8 describes these parameters.
Address Translation Table Contents
The address translation table in the Qsys design flow IP Compiler for PCI Express
parameter editor is valid only for the fixed translation table configuration. The table
provides information for translating Avalon-MM addresses to PCI Express addresses.
The number of address pages available in the table is the number of address pages
you specify in the Address Translation section of the parameter editor.
The table entries specify the PCI Express base addresses of memory that the bridge
can access. In translation of Avalon-MM addresses to PCI Express addresses, the
upper bits of the Avalon-MM address are replaced with part of a specific entry. The
most significant bits of the Avalon-MM address index the table, selecting the address
page to use for each request.
The PCIe address field comprises two parameters, bits [31:0] and bits [63:32] of the
address. The Size of address pages value you specify in the Address Translation
section of the parameter editor determines the number of least significant bits in the
address that are replaced by the lower bits of the incoming Avalon-MM address.
Table 3–8. Avalon-MM Address Translation Settings
Parameter Value Description
Address Translation
Table Configuration
Dynamic translation
table,
Fixed translation
table
Sets Avalon-MM-to-PCI Express address translation scheme to
dynamic or fixed.
Dynamic translation table—Enables application software to write
the address translation table contents using the control register
access slave port. On-chip memory stores the table. Requires that
the Avalon-MM CRA Port be enabled. Use several address
translation table entries to avoid updating a table entry before
outstanding requests complete. This option supports up to 512
address pages.
Fixed translation table—Configures the address translation table
contents to hardwired fixed values at the time of system generation.
This option supports up to 16 address pages.
Number of address
pages 1, 2, 4, 8, 16, 32, 64,
128, 256, 512
Specifies the number of PCI Express base address pages of memory
that the bridge can access. This value corresponds to the number of
entries in the address translation table. The Avalon address range is
segmented into one or more equal-sized pages that are individually
mapped to PCI Express addresses. Select the number and size of the
address pages. If you select Dynamic translation table, use several
address translation table entries to avoid updating a table entry before
outstanding requests complete. Dynamic translation table supports up
to 512 address pages, and fixed translation table supports up to 16
address pages.
Size of address pages 4 Kbyte–4 Gbytes
Specifies the size of each PCI Express memory segment accessible by
the bridge. This value is common for all address translation entries.