Altera IP Compiler for PCI Express - Manual (Page 251)

Chapter 15: Testbench and Design Example 15–19
Test Driver Module
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
For a root port Verilog HDL file, see:
<variation_name>_examples/rootport/testbench/altpcietb_bfm_driver_rp.v
The BFM test driver module performs the following steps in sequence:
1. Configures the root port and endpoint configuration spaces, which the BFM test
driver module does by calling the procedure ebfm_cfg_rp_ep, which is part of
altpcietb_bfm_configure
.
2. Finds a suitable BAR to access the example endpoint design control register space.
Either BARs 2 or 3 must be at least a 256-byte memory BAR to perform the DMA
channel test. The find_mem_bar procedure in the altpcietb_bfm_driver_chaining
does this.
3. If a suitable BAR is found in the previous step, the driver performs the following
tasks:
■ DMA read—The driver programs the chaining DMA to read data from the
BFM shared memory into the endpoint memory. The descriptor control fields
(
Table 15–6 ) are specified so that the chaining DMA completes the following
steps to indicate transfer completion:
a. The chaining DMA writes the EPLast bit of the “Chaining DMA Descriptor
Table” on page 15–17 after finishing the data transfer for the first and last
descriptors.
b. The chaining DMA issues an MSI when the last descriptor has completed.
■ DMA write—The driver programs the chaining DMA to write the data from its
endpoint memory back to the BFM shared memory. The descriptor control
fields (
Table 15–6 ) are specified so that the chaining DMA completes the
following steps to indicate transfer completion:
c. The chaining DMA writes the EPLast bit of the “Chaining DMA Descriptor
Table” on page 15–17 after completing the data transfer for the first and last
descriptors.
d. The chaining DMA issues an MSI when the last descriptor has completed.
e. The data written back to BFM is checked against the data that was read from
the BFM.
f. The driver programs the chaining DMA to perform a test that demonstrates
downstream access of the chaining DMA endpoint memory.
DMA Write Cycles
The procedure dma_wr_test used for DMA writes uses the following steps:
1. Configures the BFM shared memory. Configuration is accomplished with three
descriptor tables ( Table 15–14 , Table 15–15 , and Table 15–16 ).
Table 15–14. Write Descriptor 0
Offset in BFM
Shared Memory
Value Description
DW0 0x810 82
Transfer length in DWORDS and control bits as described in
Table 15–6 on page 15–14
DW1 0x814 3 Endpoint address