Altera IP Compiler for PCI Express - Manual (Page 363)

Chapter : Info–3
Revision History
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
December
2010
10.1
■ Added support for the following new features in Stratix V devices:
■ 256-bit interface
■ Simulation support
■ Added support for soft IP implementation of PCI Express IP core in Cyclone IV GX with
Avalon-ST interface
■ Added support for Arria II GZ with Avalon-ST interface
■ Revised description of reset logic to reflect changes in the implementation. Added new free
running fixedclk, busy_reconfig_altgxb_reconfig, and
reset_reconfig_altgxb_reconfig
signals to hard IP implementation in Arria II GX,
Arria II GZ, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX devices.
■ Added CBB module to testbench to provide push button access for CBB testing
■ The ECC error signals, derr_*, r2c_err0, and rx_st_err<0> are not available in the hard IP
implementation of the PCI Express IP core for Arria II GX devices.
■ Corrected Type field of the Configuration Write header in Table A–13 on page A–4. The value
should be 5’b00101, not 5’b00010.
■ Improved description of AVL_IRQ_INPUT_VECTOR in Table 6–13 on page 6–7.
■ Corrected size of tx_cred signal for soft IP implementation in Figure 5–3 on page 5–4. It is
36 bits, not 22 bits.
■ Clarified behavior of the rx_st_valid signal in the hard IP implementation of Arria II GX,
Cyclone IV GX, HardCopy, and Stratix IV GX devices in Figure 5–2 on page 5–3.
■ Added fact that tx_st_err is not available for packets that are 1 or 2 cycles long in
Table 5–4 on page 5–12.
■ Updated Figure 5–26 on page 5–29 and Figure 5–28 on page 5–30 to include pld_clk in
64-bit and 128-bit mode. Also added discussion of .sdc timing constraints for the
tl_cfg_ctl_wr and tl_cfg_sts_wr . .
■ Corrected bit definitions for Max Payload and Max Read Request Size in Table 5–14 on
page 5–31.
■ Corrected description of dynamic reconfiguration in Chapter 13, Reconfiguration and Offset
Cancellation. Link is brought down by asserting pcie_reconfig_rstn, not npor.
July 2010 10.0
■ Added support for Stratix V GX and GT devices.
■ Added 2 new variants:
■ Support for an integrated PCI Express hard IP endpoint that includes all of the reset and
calibration logic.
■ Support for a basic PCI Express completer-only endpoint with fixed transfer size of a
single dword. Removed recommended frequencies for calibration and reconfiguration
clocks. Referred reader to appropriate device handbook.
■ Added parity protection in Stratix V GX devices.
■ Added speed grade information for Cyclone IV GX and included a second entry for
Cyclone IV GX running at 62.5 MHz in Table 1–9 on page 1–13.
■ Clarified qword alignment for request and completion TLPs for Avalon-ST interfaces.
Date Version Changes Made SPR