Altera IP Compiler for PCI Express - Manual (Page 235)

Chapter 15: Testbench and Design Example 15–3
Endpoint Testbench
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces
of the root port and endpoints or the serial interface. The testbench design does not
allow more than one PCI Express link to be simulated at a time.
Figure 15–1 presents a
high level view of the testbench.
The top-level of the testbench instantiates four main modules:
■ < variation name>_example_chaining_pipen1b—This is the example endpoint
design that includes your variation of the IP core variation. For more information
about this module, refer to
“Chaining DMA Design Example” on page 15–6 .
■ altpcietb_bfm_rp_top_x8_pipen1b —This is the root port PCI Express BFM. For
detailed information about this module, refer to “Root Port BFM” on page 15–26 .
■ altpcietb_pipe_phy —There are eight instances of this module, one per lane. These
modules interconnect the PIPE MAC layer interfaces of the root port and the
endpoint. The module mimics the behavior of the PIPE PHY layer to both MAC
interfaces.
■ altpcietb_bfm_driver_chaining —This module drives transactions to the root port
BFM. This is the module that you modify to vary the transactions sent to the
example endpoint design or your own design. For more information about this
module, refer to
“Root Port Design Example” on page 15–22 .
In addition, the testbench has routines that perform the following tasks:
■ Generates the reference clock for the endpoint at the required frequency.
■ Provides a reset at start up.
Figure 15–1. Testbench Top-Level Module for Endpoint Designs
Testbench Top Level (<variation name>_testbench)
Endpoint Example Design PIPE Interconnection
Module (x8)
(altpcierd_pipe_phy)
Root Port BFM
(altpcietb_bfm_rp_top_x8_pipen1b)
Test Driver Module
(altpcietb_bfm_driver_chaining)
Chaining DMA
<variation name>_example_
chaining_pipen1b.v