Altera IP Compiler for PCI Express - Manual (Page 87)

August 2014 Altera Corporation IP Compiler for PCI Express User Guide
5. IP Core Interfaces
This chapter describes the signals that are part of the IP Compiler for PCI Express for
each of the following primary configurations:
■ Signals in the Hard IP Implementation Root Port with Avalon-ST Interface Signals
■ Signals in the Hard IP Implementation Endpoint with Avalon-ST Interface
■ Signals in the Soft IP Implementation with Avalon-ST Interface
■ Signals in the Soft or Hard Full-Featured IP Core with Avalon-MM Interface
■ Signals in the Qsys Hard Full-Featured IP Core with Avalon-MM Interface
■ Signals in the Completer-Only, Single Dword, IP Core with Avalon-MM Interface
■ Signals in the Qsys Completer-Only, Single Dword, IP Core with Avalon-MM
Interface
1 Altera does not recommend the Descriptor/Data interface for new designs.
Avalon-ST Interface
The main functional differences between the hard IP and soft IP implementations
using an Avalon-ST interface are the configuration and clocking schemes. In addition,
the hard IP implementation offers a 128-bit Avalon-ST bus for some configurations. In
128-bit mode, the streaming interface clock, pld_clk, is one-half the frequency of the
core clock, core_clk, and the streaming data width is 128 bits. In 64-bit mode, the
streaming interface clock, pld_clk, is the same frequency as the core clock, core_clk,
and the streaming data width is 64 bits.
Figure 5–1 , Figure 5–2 , and Figure 5–3 illustrate the top-level signals for IP cores that
use the Avalon-ST interface.
August 2014
<edit Part Number variable in chapter>