Altera IP Compiler for PCI Express - Manual (Page 75)

Chapter 4: IP Core Architecture 4–17
PCI Express Avalon-MM Bridge
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Reverse Parallel Loopback
In Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX devices, the IP
Compiler for PCI Express hard IP implementation supports a reverse parallel
loopback path you can use to test the IP Compiler for PCI Express endpoint link
implementation from a PCI Express root complex. When this path is enabled, data
that the IP Compiler for PCI Express endpoint receives on the PCI Express link passes
through the RX PMA and the word aligner and rate matching FIFO buffer in the RX
PCS as usual. From the rate matching FIFO buffer, it passes along both of the
following two paths:
■ The usual data path through the IP Compiler for PCI Express hard IP block.
■ A reverse parallel loopback path to the TX PMA block and out to the PCI Express
link. The input path to the TX PMA is gated by a multiplexor that controls whether
the TX PMA receives data from the TX PCS or from the reverse parallel loopback
path.
f For information about the reverse parallel loopback mode and an illustrative block
diagram, refer to “PCIe (Reverse Parallel Loopback)” in the
Transceiver Architecture in
Arria II Devices chapter of the Arria II Device Handbook, “Reverse Parallel Loopback” in
the Cyclone IV Transceivers Architecture chapter of the Cyclone IV Device Handbook, or
“PCIe Reverse Parallel Loopback” in the Transceiver Architecture in Stratix IV Devices
chapter of the Stratix IV Device Handbook.
For information about configuring and using the reverse parallel loopback path for
testing, refer to
“Link and Transceiver Testing” on page 17–3 .
PCI Express Avalon-MM Bridge
The IP Compiler for PCI Express uses the IP Compiler for PCI Express Avalon-MM
bridge module to connect the PCI Express link to the system interconnect fabric. The
bridge facilitates the design of PCI Express endpoints that include Qsys components.
The full-featured PCI Express Avalon-MM bridge provides three possible Avalon-MM
ports: a bursting master, an optional bursting slave, and an optional non-bursting
slave. The PCI Express Avalon-MM bridge comprises the following three modules:
■ TX Slave Module—This optional 64-bit bursting, Avalon-MM dynamic addressing
slave port propagates read and write requests of up to 4 KBytes in size from the
system interconnect fabric to the PCI Express link. The bridge translates requests
from the interconnect fabric to PCI Express request packets.
■ RX Master Module—This 64-bit bursting Avalon-MM master port propagates PCI
Express requests, converting them to bursting read or write requests to the system
interconnect fabric.
■ Control Register Access (CRA) Slave Module—This optional, 32-bit Avalon-MM
dynamic addressing slave port provides access to internal control and status
registers from upstream PCI Express devices and external Avalon-MM masters.
Implementations that use MSI or dynamic address translation require this port.