Altera IP Compiler for PCI Express - Manual (Page 37)

August 2014 Altera Corporation IP Compiler for PCI Express User Guide
3. Parameter Settings
You customize the IP Compiler for PCI Express by specifying parameters in the IP
Compiler for PCI Express parameter editor, which you access from the IP Catalog.
Some IP Compiler for PCI Express variations are supported in only one or two of the
design flows. Soft IP implementations are supported only in the Quartus II IP Catalog.
For more information about the hard IP implementation variations available in the
different design flows, refer to
Table 1–5 on page 1–6 .
This chapter describes the parameters and how they affect the behavior of the IP core.
The IP Compiler for PCI Express parameter editor that appears in the Qsys flow is
different from the IP Compiler for PCI Express parameter editor that appears in the
other two design flows. Because the Qsys design flow supports only a subset of the
variations supported in the other two flows, and generates only hard IP
implementations with specific characteristics, the Qsys flow parameter editor
supports only a subset of the parameters described in this chapter.
Parameters in the Qsys Design Flow
The following sections describe the IP Compiler for PCI Express parameters available
in the Qsys design flow. Separate sections describe the parameters available in
different sections of the IP Compiler for PCI Express parameter editor.
The available parameters reflect the fact that the Qsys design flow supports only the
following functionality:
■ Hard IP implementation
■ Native endpoint, with no support for:
■ I/O space BAR
■ 32-bit prefetchable memory
■ 16 Tags
■ 1 Message Signaled Interrupt (MSI)
■ 1 virtual channel
■ Up to 256 bytes maximum payload
August 2014
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