Altera IP Compiler for PCI Express - Manual (Page 319)

August 2014 Altera Corporation IP Compiler for PCI Express User Guide
B. IP Compiler for PCI Express Core with
the Descriptor/Data Interface
This chapter describes the IP Compiler for PCI Express variation that employs the
legacy descriptor/data interface. It includes the following sections:
■ Descriptor/Data Interface
■ Incremental Compile Module for Descriptor/Data Examples
1
Altera recommends choosing the Avalon-ST or Avalon-MM interface for all new
designs for compatibility with the hard IP implementation of the IP Compiler for PCI
Express.
Descriptor/Data Interface
When you generate an IP Compiler for PCI Express endpoint with the
descriptor/data interface, the parameter editor generates the transaction, data link,
and PHY layers.
Figure B–1 illustrates this interface.
RX and TX ports use a data/descriptor style interface, which presents the application
with a descriptor bus containing the TLP header and a separate data bus containing
the TLP payload. A single-cycle-turnaround handshaking protocol controls the
transfer of data.
Figure B–1. PCI Express IP core with Descriptor/Data Interface
Tx
Rx
Transaction Layer Data Link Layer Physical Layer
IP Compiler for PCI Express
To Application Layer To Link
tx_desc
tx_data
rx_desc
rx_data
With information sent
by the application
layer, the transaction
layer generates a TLP,
which includes a
header and, optionally,
a data payload. The data link layer
ensures packet
integrity, and adds a
sequence number and
link cyclic redundancy
code (LCRC) check to
the packet. The physical layer
encodes the packet
and transmits it to the
receiving device on the
other side of the link.
The transaction layer
disassembles the
transaction and
transfers data to the
application layer in a
form that it recognizes. The data link layer
verifies the packet's
sequence number and
checks for errors. The physical layer
decodes the packet
and transfers it to the
data link layer.
August 2014
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