Altera IP Compiler for PCI Express - Manual (Page 242)

15–10 Chapter 15: Testbench and Design Example
Chaining DMA Design Example
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
The following modules are included in the design example and located in the
subdirectory <variation name>_example/chaining_dma:
■ <variation name>_example_pipen1b—This module is the top level of the example
endpoint design that you use for simulation. This module is contained in the
following files produced by the parameter editor:
<variation name>_example_chaining_top.vhd, and
<variation name>_example_chaining_top.v
This module provides both PIPE and serial interfaces for the simulation
environment. This module has two debug ports named test_out_icm (which is
either the test_out_icm signal from the Incremental Compile Module in
descriptor/data example designs or the test_out signal from the IP core in
Avalon-ST example designs) and test_in. Refer to
“Test Interface Signals—
Hard IP Implementation” on page 5–59 which allow you to monitor and control
internal states of the IP core.
For synthesis, the top level module is <variation_name>_example_chaining_top.
This module instantiates the module <variation name>_example_pipen1b and
propagates only a small sub-set of the test ports to the external I/Os. These test
ports can be used in your design.
■ <variation name>.v or <variation name>.vhd—The parameter editor creates this
variation name module when it generates files based on the parameters that you
set. For simulation purposes, the IP functional simulation model produced by the
parameter editor. The IP functional simulation model is either the <variation
name>.vho or <variation name>.vo file. The Quartus II software uses the associated
<variation name>.vhd or <variation name>.v file during compilation. For
information on producing a functional simulation model, see the
Chapter 2,
Getting Started .
The chaining DMA design example hierarchy consists of these components:
■ A DMA read and a DMA write module
■ An on-chip endpoint memory (Avalon-MM slave) which uses two Avalon-MM
interfaces for each engine
■ The RC slave module is used primarily for downstream transactions which target
the endpoint on-chip buffer memory. These target memory transactions bypass the
DMA engines. In addition, the RC slave module monitors performance and
acknowledges incoming message TLPs.
Each DMA module consists of these components:
■ Control register module—The RC programs the control register (four dwords)
to start the DMA.
■ Descriptor module—The DMA engine fetches four dword descriptors from
BFM shared memory which hosts the chaining DMA descriptor table.
■ Requester module—For a given descriptor, the DMA engine performs the
memory transfer between endpoint memory and the BFM shared memory.