Eia-530a port interface – Paradyne T1 T1 Access Mux 926x User Manual
Page 280
Cables, Connectors, and Pin Assignments
E-6
9161-A2-GH30-30
April 1998
EIA-530A Port Interface
The following table shows the EIA-530A circuit and pin assignments that are
supported for a port connector/ interface ( Port 1 or Port 2 ).
Signal
Circuit
Mnemonic
ITU/
CCITT #
Direction
25-Pin
Pin #
Shield
—
—
—
1
Transmitted Data ( TXD )
BA
103
To DCE
2 (A)
14 (B)
Received Data ( RXD )
BB
104
From DCE
3 (A)
16 (B)
Request to Send ( RTS )
CA
105
To DCE
4 (A)
19 (B)
Clear to Send ( CTS )
CB
106
From DCE
5 (A)
13 (B)
Data Set (or DCE ) Ready
( DSR )
CC
107
From DCE
6
Signal Ground/Common ( SG )
AB
102A
—
7
Received Line Signal Detector
( RLSD or LSD )
CF
109
From DCE
8 (A)
10 (B)
Transmit Signal Element
Timing (TXC – DTE Source)
DA
113
To DCE
11 (B)
24 (A)
Transmitter Signal Element
Timing ( TXC – DCE Source)
DB
114
From DCE
12 (B)
15 (A)
Receiver Signal Element
Timing ( RXC – DCE Source )
DD
115
From DCE
17 (A)
9 (B)
Local Loopback ( LL )
LL
141
To DCE
18
Data Terminal (or DTE )
Ready ( DTR )
CD
108/1, /2
To DCE
20
Remote Loopback ( RL )
RL
140
To DCE
21
Signal Common
AC
102B
—
22, 23
Test Mode Indicator ( TM )
TM
142
From DCE
25