Panasonic MN103001G/F01K - Manual (Page 105)

Operating Mode
5-3
5.2 Reset Mode
• The mode in which the reset (RST) pin is active (“L” level) is called “Reset Mode”.
• When the reset pin is low, the chip is reset (initialized) internally. When the reset pin makes the transition to
high, the oscillation stabilization wait time is started by an internal 18-bit (when CKSEL pin = “H”) or 19-bit
(when CKSEL pin = “L”) binary counter based on the oscillation clock.
The oscillation stabilization wait time t
OSCW
for oscillation frequency f
OSC
[MHz] is:
t
OSCW
= 2 n / (f
OSC
x 10 3 ) [ms]
n = 18 (when CKSEL pin = “H”) or 19 (when CKSEL pin = “L”)
In other words, when CKSEL pin = “H” and f
OSC
= 15[MHz]:
t
OSCW
= 17.476 [ms]
• Table 5-2-1 shows the status of the internal registers immediately after a reset.
Table 5-2-1 Status of Internal Registers Immediately after a Reset
PC x'40000000
D3 to D0 Undefined
SP Undefined
A3 to A0 Undefined
MDR Undefined
LIR Undefined
LAR Undefined
PSW x'0000
• Internal reset is canceled after completion of oscillation stabilization wait time, and the microcontroller changes
to the normal operation mode.