Panasonic MN103001G/F01K - Manual (Page 52)

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CPU
2.5.3 Interrupt Types
The three types of interrupts are listed below:
[Reset interrupt]
The reset interrupt is the interrupt with the highest priority level, and is generated by setting the RST pin to "L"
level. As a result of the reset interrupt, the registers, etc., are initialized. When the RST pin goes to "H" level, the
microcontroller waits until the oscillation of the internal clock stabilizes, and then begins executing program
instructions starting from address x'40000000.
[Non-maskable Interrupts]
Non-maskable interrupts are accepted regardless of the PSW interrupt enable (IE) and interrupt mask level IM2 to
IM0 values. These interrupts include external pin non-maskable interrupt, watchdog timer overflow interrupt and
system error interrupt.
When a non-maskable interrupt is accepted, control transfers to an interrupt processing program located at x'40000008
or beyond.
The interrupt handler accesses NMICR to analyze the interrupt factor, performs interrupt processing, cancels the
interrupt factor, and then returns to the normal program using the RTI instruction.
External pin non-maskable interrupt
External pin non-maskable interrupt is generated when the NMIRQ pin goes to "L" level. If an external pin
non-maskable interrupt is generated, the external non-maskable interrupt request flag (NMIF) in the non-
maskable interrupt control register (NMICR) is set to "1".
Watchdog timer overflow interrupt
Watchdog timer overflow interrupt occurs when the watchdog timer count operation control flag (WDCNE)
in the watchdog timer control register (WDCTR) is "1" and the watchdog timer overflows. If a watchdog
interrupt is generated, the watchdog timer overflow interrupt request flag (WDIF) in the non-maskable interrupt
control register (NMICR) is set to "1".
System error interrupt
System error interrupt occurs when an unaligned memory access or an unimplemented instruction is executed
or other fatal error occurs. If a system error interrupt is generated, the system error interrupt request flag
(SYSEF) in the non-maskable interrupt control register (NMICR) is set to "1".
Note: Do not change the interrupt enable (IE) in PSW during non-maskable interrupt processing.