Panasonic MN103001G/F01K - Manual (Page 218)

Interrupt Controller
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9.6 Description of Operation
The following interrupt processing is performed.
• Non-maskable interrupts NMIRQ pin interrupt
Watchdog timer overflow interrupt
System error interrupt
• Level interrupts
• Internal interrupts Peripheral interrupts from timer, serial, A/D
• External interrupts External pin interrupts x 8
In the event of a level interrupt, an interrupt group determination is made, and an interrupt request is sent to the
CPU.
Once the interrupt signal is received, it is determined to be either a non-maskable interrupt or a level interrupt.
If it is a level interrupt, the interrupt group is determined by deciding to which group the interrupt factor belongs.
Once the interrupt group is determined, the interrupt request is sent by manipulating the interrupt control register
(GnICR) for that group in order to notify the CPU of the interrupt group level. The interrupt group number is also
set in the interrupt acceptance group register (IAGR).
The interrupt level of a group can be determined by reading the interrupt priority level register LV2 to 0 in the
interrupt control register (GnICR).
If multiple level interrupt signals are received, the groups to which each belongs is determined and then the interrupt
group with the highest priority level is selected. If the group levels are the same, the group with the smallest group
number is selected.
The processing described above is not performed in the case of a non-maskable interrupt; instead, the non-maskable
interrupt request is simply sent to the CPU.